MB81ES171625 Fujitsu Media Devices Limited, MB81ES171625 Datasheet - Page 17

• Manufacturer Part Number: MB81ES171625
• Description: SINGLE DATA RATE I/F FCRAM Consumer/Embedded Application Specific Memory for SiP
• Manufacturer: Fujitsu Media Devices Limited

7. Bank Select (BA)
8. Data Inputs and Outputs (DQ
9. Data I/O Mask (DQM
10. Burst Mode Operation
(1) Burst Type
(2) Burst Mode Termination and Method of Next Stage Set
This SDR I/F FCRAM has two banks.
Bank selection by BA occurs at Bank Active command (ACTV) followed by read (READ or READA) , write (WRIT
or WRITA) , and precharge commands (PRE or PALL) .
Input data is latched and written into the memory at the clock following the write command input. Data output is
obtained by the following conditions followed by a read command input :
The polarity of the output data is identical to that of input data. Data is valid between access time (determined
by the three conditions above) and the next positive clock edge (t
Refer to “ AC CHARACTERISTICS”.
DQM is an active high enable input and has an output disable and input mask function. During burst cycle and
when DQM High is latched by a clock, input is masked at the same clock and output will be masked at CL later
while internal burst counter will increment by one or will go to the next stage depending on the burst type.
The burst mode provides faster memory access. The burst mode is implemented by keeping the same Row
address and by automatically strobing column address. Access time and cycle time of Burst mode is specified
as t
which defines burst type and the burst count length of 1, 2, 4, 8 bits of boundary or full column. In order to
terminate or move from the current burst mode to the next stage while the remaining burst count is more than
1, the following combinations will be required :
The burst type can be selected either sequential or interleave mode if burst length is 2, 4 or 8. The sequential
mode is an incremental decoding scheme within a boundary address to be determined by burst length, it assigns
least significant address (
first access of column address is even (0) , the next address will be odd (1) , or vice-versa.
Current Stage
1 to the previous (or initial) address until reaching the end of boundary address and then wraps around to the
Burst Read
Burst Read
Burst Read
Burst Write
Burst Write
Burst Write
t
t
t
RAC
CAC
AC
CAC
/t
; from the bank active command when t
; from the read command when t
; from the rising edge of clock after t
AC
and t
CK
, respectively. The internal column address counter operation is determined by a mode register
Next Stage
Burst Read
Burst Write
Burst Write
Burst Read
Precharge
Precharge
1
to DQM
0) . The interleave mode is a scrambled decoding scheme for A
0
15
/DQM
to DQ
RCD
is greater than t
3
2nd Step
RAC
1st Step
to DQM
0
/DQ
RCD
and t
MB81ES171625/173225-15-X
(Min) is satisfied. (This parameter is reference only.)
31
CAC
to DQ
Method (Assert the following command)
0
)
.
Read Command
Mask Command (Normally 3 clock cycles)
Write Command after l
Write Command
Read Command
Precharge Command
Precharge Command
RCD
0
)
(Min) at CL
OH
) .
1.
OWD
0
through A
2
. If the
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