MB85RS256A Fujitsu, MB85RS256A Datasheet - Page 10

• Manufacturer Part Number: MB85RS256A
• Description: 256 K (32 K X 8) Bit SPI
• Manufacturer: Fujitsu

MB85RS256A
■ BLOCK PROTECT
■ WRITING PROTECT
■ HOLD OPERATION
10
CS
SCK
HOLD
Writing protect block is configured by the WRITE command with BP1, BP0 value of the status register.
Writing operation of the WRITE command and the WRSR command are protected with the value of WEL,
WPEN, WP as shown in the table.
Hold status is retained without aborting a command if HOLD is “L” while CS is “L”. The timing for starting
and ending hold status depends on the SCK to be “H” or “L” when a HOLD pin input is transited as shown
in the diagram below. Arbitrary command operation is interrupted in hold status, SCK and SI inputs become
don’t care. And, SO becomes High-Z while reading command (RDSR, READ) . If CS is risen with hold status,
a command is aborted and device is reset.
WEL
0
1
1
1
BP1
0
0
1
1
WPEN
X
0
1
1
BP0
WP
X
X
0
1
0
1
0
1
Hold Condition
Protected Blocks
None
6000
4000
0000
Protected
Protected
Protected
Protected
H
H
H
to 7FFF
to 7FFF
to 7FFF
Protected Block
H
H
H
(upper 1/4)
(upper 1/2)
(all)
Unprotected Blocks
Unprotected
Unprotected
Unprotected
Hold Condition
Protected
DS501-00007-0v01-E
Status Register
Unprotected
Unprotected
Protected
Protected