MB85RS256A Fujitsu, MB85RS256A Datasheet - Page 9

• Manufacturer Part Number: MB85RS256A
• Description: 256 K (32 K X 8) Bit SPI
• Manufacturer: Fujitsu

• READ
• WRITE
DS501-00007-0v01-E
CS
SCK
SI
SO
CS
SCK
SI
SO
The READ command reads FRAM memory cell array data. Arbitrary 16 bits address and op-code of READ
are input to SI. The most significant address bit is invalid. Then, 8-cycle clock is input to SCK. SO is output
synchronously to the falling edge of SCK. While reading, the SI value is invalid. When CS is risen, the READ
command is completed, but keep on reading address with automatic increment is enabled by continuously
sending clock for 8 cycles each to SCK before CS is risen. When it reaches the most significant address, it
rolls over to come back to the starting address, and reading cycle keeps on infinitely.
The WRITE command writes data to FRAM memory cell array. WRITE op-code, arbitrary 16 bits of address
and 8 bits of writing data are input to SI. The most significant address bit is invalid. When 8 bits of writing
data is input, data is written to FRAM memory cell array. Risen CS will terminate the WRITE command, but
if you continue sending the writing data for 8 bits each before CS is risen, it is possible to continue writing
with automatic address increment. When it reaches the most significant address, it rolls over, comes back
to the starting address, and writing cycle can be continued infinitely.
0
0
0
0
1
1
0
0
2
2
0
0
OP-CODE
OP-CODE
3
0
3
0
4
0
4
0
5
0
5
0
1
1
6
6
1
0
7
7
MSB
MSB
X
X
8
8
14
14
9
9
13
13
10
10
12
12
11
11
11
11
12
12
16-bit Address
16-bit Address
10
High-Z
10
High-Z
13
13
18
5
18
5
19
4
19
4
3
20
20
3
21
2
21
2
22
1
22
1
LSB
LSB
0
23
23
0
MSB
MSB
24
7
24
7
MB85RS256A
25
25
6
6
26
5
26
5
Invalid
Data In
27
4
27
4
Data Out
28
3
28
3
29
29
2
2
30
1
30
1
LSB
LSB
31
0
31
0
Invalid
9