MB85RS256A Fujitsu, MB85RS256A Datasheet - Page 2

• Manufacturer Part Number: MB85RS256A
• Description: 256 K (32 K X 8) Bit SPI
• Manufacturer: Fujitsu

MB85RS256A
■ PIN ASSIGNMENT
■ PIN FUNCTIONAL DESCRIPTIONS
2
Pin No. Pin Name
1
3
7
6
5
2
8
4
HOLD
GND
SCK
WP
V
CS
SO
SI
CC
Chip Select
This is an input pin to make chips select. When CS is “H”, device is in deselect (standby)
status as long as device is not write status internally, and SO becomes High-Z. Other in-
puts from pins are ignored for this time. When CS is “L”, device is in select (active) status.
CS has to be “L” before inputting op-code.
Write Protect
This is a pin to control writing to a status register. When WP is “L”, writing to a status
register is not operated.
Hold
This pin is used to interrupt serial input/output without making chips deselect. When
HOLD is “L”, hold operation is activated, SO becomes High-Z, SCK and SI become don’t
care. While the hold operation, CS has to be retained “L”.
Serial Clock
This is a clock input pin to input/output serial data. SI is loaded synchronously to a rising
edge, SO is output synchronously to a falling edge.
Serial Data Input
This is an input pin of serial data. This inputs op-code, address, and writing data.
Serial Data Output
This is an output pin of serial data. Reading data of FRAM memory cell array and status
register data are output. This is High-Z during standby.
Supply Voltage
Ground
GND
WP
SO
CS
1
2
3
4
(FPT-8P-M02)
(TOP VIEW)
Functional description
8
7
6
5
HOLD
SCK
SI
V
CC
DS501-00007-0v01-E