MB85RS256A Fujitsu, MB85RS256A Datasheet - Page 6

• Manufacturer Part Number: MB85RS256A
• Description: 256 K (32 K X 8) Bit SPI
• Manufacturer: Fujitsu

MB85RS256A
■ STATUS REGISTER
■ OP-CODE
6
MB85RS256A accepts 6 kinds of command specified in op-code. Op-code is a code composed of 8 bits
shown in the table below. Do not input invalid codes other than those codes. If CS is risen while inputting
op-code, the command are not performed.
Bit No.
6 to 4
7
3
2
1
0
WRITE
WREN
WRSR
RDSR
Name
READ
WRDI
Bit Name
WPEN
WEL
BP1
BP0
⎯
0
Set Write Enable Latch
Reset Write Enable Latch
Read Status Register
Write Status Register
Read Memory Code
Write Memory Code
Status Register Write Protect
This is a bit composed of nonvolatile memories (FRAM). WPEN is related
to WP input to protect writing to a status register (refer to “■ WRITING
PROTECT”). Writing with the WRSR command and reading with the
RDSR command are possible.
Not Used Bits
These are bits composed of nonvolatile memories, writing with the WRSR
command is possible, and “000” is written before shipment. These bits are
not used but they are read with the RDSR command.
Block Protect
This is a bit composed of nonvolatile memory (FRAM). This defines block
size for writing protect with the WRITE command (refer to “■ BLOCK
PROTECT”). Writing with the WRSR command and reading with the
RDSR command are possible.
Write Enable Latch
This indicates FRAM memory and status register are writable. The WREN
command is for setting, and the WRDI command is for resetting. With the
RDSR command, reading is possible but writing is not possible with the
WRSR command. WEL is reset after the following operations.
This is a bit fixed to “0”.
The time when power is up.
The time when the WRDI command is input.
The time when the WRSR command is input.
The time when the WRITE command is input.
Description
Function
DS501-00007-0v01-E
0000 0110
0000 0100
0000 0101
0000 0001
0000 0011
0000 0010
Op-code
B
B
B
B
B
B