MB85RS256A Fujitsu, MB85RS256A Datasheet - Page 8

• Manufacturer Part Number: MB85RS256A
• Description: 256 K (32 K X 8) Bit SPI
• Manufacturer: Fujitsu

MB85RS256A
• RDSR
• WRSR
8
SCK
SI
SO
CS
CS
SCK
SI
SO
The RDSR command reads status register data. After op-code of RDSR is input to SI, 8-cycle clock is input
to SCK. The SI value is invalid for this time. SO is output synchronously to a falling edge of SCK. Continuously
reading status register is enabled by keep on sending SCK before rising CS with the RDSR command.
The WRSR command writes data to the nonvolatile memory bit of status register. After performing WRSR
op-code to a SI pin, 8 bits writing data is input. WEL (Write Enable Latch) is not able to be written with WRSR
command. a SI value correspondent to bit 1 is ignored. Bit 0 of the status register is fixed to “0” and cannot
be written. The SI value corresponding to bit 0 is ignored.
0
0
0
0
0
0
1
1
High-Z
0
0
2
2
Instruction
0
0
3
3
0
0
4
4
1
0
5
5
0
0
6
6
High-Z
1
1
7
7
MSB
MSB
7
0
0
6
1
1
5
Data In
2
2
4
3
3
Data Out
Invalid
3
4
4
2
5
5
DS501-00007-0v01-E
1
6
6
LSB
LSB
0
7
7
Invalid