GS1532 Gennum Corporation, GS1532 Datasheet - Page 12

• Manufacturer Part Number: GS1532
• Description: Serializer For HD-SDI, Sd-sdi & DVB-ASI. 3.3/1.8V Supply.
• Manufacturer: Gennum Corporation

1.2 PIN DESCRIPTIONS (Continued)
GENNUM CORPORATION
15, 16, 17
NUMBER
4, 5, 6, 7,
8, 10, 14,
66, 70,
31, 65,
73,74
PIN
67
68
69
72
75
76
77
78
79
80
71
DETECT_TRS
CORE_GND
VCO_GND
VCO, VCO
VCO_VCC
LB_CONT
LOCKED
CP_GND
CP_CAP
NAME
PCLK
RSV1
RSV2
LF
(Continued)
(Continued)
(Continued)
Synchronous
Synchronous
Synchronous
with PCLK
TIMING
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Non
Non
-
-
Input Power
Input Power
Output
Output
Output
Output
Power
Power
TYPE
Input
Input
Input
Input
Input
-
-
12
CONTROL SIGNAL INPUT
Signal levels are LVCMOS / LVTTL compatible.
Used to select external HVF timing mode or TRS extraction timing
mode.
When DETECT_TRS is LOW, the device will extract all internal
timing information from the supplied H:V:F timing signals.
When DETECT TRS is HIGH, the device will extract all internal
timing information from TRS signals embedded in the supplied
video stream.
GND connection - Digital logic
PARALLEL DATA BUS CLOCK
Signal levels are LVCMOS / LVTTL compatible.
HDTV 20 bit mode
HDTV 10 bit mode
SDTV 20 bit mode
SDTV 10 bit mode
STATUS SIGNAL Output
Signal levels are LVCMOS / LVTTL compatible.
This signal will be HIGH when the PLL has achieved lock to the
supplied PCLK signal.
This pin will be LOW under all other conditions.
When this signal is LOW, the serial digital output SDO / SDO will
be forced to a logic level LOW.
Differential inputs for the external VCO. For single ended devices
such as the GO1525, VCO should be decoupled to GND.
GND pin for the voltage controlled oscillator. (Internal regulator
output)
Power supply for the voltage controlled oscillator 2.5V DC supplied
by the device to the external VCO. (Internal regulator output).
Control voltage to external VCO.
PLL lock time constant capacitor connection.
CONTROL SIGNAL INPUT
Control voltage to set the loop bandwidth of the PLL.
GND pin for the charge pump.
Reserved - connect to PD_GND.
Reserved - connect to CORE_GND.
PCLK = 74.25MHz (or 74.25/1.001MHz)
PCLK = 148. 5MHz (or 148.5/1.001MHz)
PCLK = 13.5MHz
PCLK = 27MHz
DESCRIPTION
21498 - 0