GS1532 Gennum Corporation, GS1532 Datasheet - Page 7

• Manufacturer Part Number: GS1532
• Description: Serializer For HD-SDI, Sd-sdi & DVB-ASI. 3.3/1.8V Supply.
• Manufacturer: Gennum Corporation

1.2 PIN DESCRIPTIONS (Continued)
GENNUM CORPORATION
NUMBER
PIN
25
26
27
28
RESET_TRST
SDOUT_TDO
JTAG/HOST
CS_TMS
NAME
(Continued)
(Continued)
(Continued)
with SCLK_TCK
with SCLK_TCK
Synchronous
Synchronous
Synchronous
Synchronous
TIMING
Non
Non
Output
TYPE
Input
Input
Input
7
CONTROL SIGNAL INPUT
Signal levels are LVCMOS / LVTTL compatible.
Used to reset the internal operating conditions to default settings
and to reset the JTAG test sequence.
Normal mode (JTAG/HOST = LOW)
When LOW, all functional blocks will be set to default conditions
and all input and output signals become high impedance including
the serial digital outputs SDO and SDO.
When HIGH, normal operation of the device resumes 10 µ sec after
the low to high transition of the RESET_TRST signal.
JTAG test mode (JTAG/HOST = HIGH)
When LOW, all functional blocks will be set to default and the JTAG
test sequence will be held reset.
When HIGH, normal operation of the JTAG test sequence resumes.
CONTROL SIGNAL INPUT
Signal levels are LVCMOS / LVTTL compatible.
Used to select JTAG Test Mode or Host Interface Mode.
When JTAG/HOST is HIGH, the CS_TMS, SDOUT_TDO, SDI_TDI
and SCLK_TCK pins are configured for JTAG test.
When JTAG/HOST is LOW, the above pins are configured for
normal host interface operation.
CONTROL SIGNAL INPUT
Signal levels are LVCMOS / LVTTL compatible.
Chip Select / Test Mode Select
When JTAG/HOST = HIGH, this pin is JTAG TMS.
When JTAG/HOST = LOW, this pin operates as the host interface
chip select and is active LOW.
CONTROL SIGNAL OUTPUT
Signal levels are LVCMOS / LVTTL compatible.
Serial Data Output / Test Data Output
When JTAG/HOST = HIGH, this pin is JTAG TDO.
When JTAG/HOST = LOW, this pin is used to read status and
configuration data from the device.
DESCRIPTION
21498 - 0