GS1532 Gennum Corporation, GS1532 Datasheet - Page 27

• Manufacturer Part Number: GS1532
• Description: Serializer For HD-SDI, Sd-sdi & DVB-ASI. 3.3/1.8V Supply.
• Manufacturer: Gennum Corporation

3.1.3 GSPI Timing
Write and read mode timing for the GSPI interface is as
shown in the following diagrams.
3.1.4 Configuration and Status Register Description
The GS1532 provides status and configuration registers.
These registers may be used to enable additional features
of
information.
The GS1532 contains the following registers:
•
•
•
•
•
All of these registers are available to the application layer
via the host interface and are all individually addressable.
Where status registers contain less than the full 16 bits of
information however, two or more registers may be
combined at a single logical address.
3.2 JTAG TEST
When the JTAG/HOST is HIGH, the host interface port will
be configured for JTAG test operation. In this mode the
SCLK, SDIN, SDOUT and CS become TCK, TDI, TDO and
TMS. In addition, the TRST pin become active.
Boundary scan testing using the JTAG interface will be
enabled in this mode.
GENNUM CORPORATION
4 VIDEO_FORMAT registers
4 RASTER_STRUCTURE registers
1 EDH_CALCULATION_RANGE register
2 DATA_FORMAT registers
1 IOPROC_DISABLE_MASK register
the
SDOUT
SCLK
SDIN
CS
device
SDOUT
SDIN
SCLK
CS
R/W
R/W
RSV
t 0
and/or
RSV
RSV
t 3
RSV
RSV
t 1
RSV
RSV
to
RSV
RSV
RSV
provide
t 2
RSV
RSV
RSV
RSV
RSV
RSV
additional
RSV
RSV
A5
A5
A4
A4
A3
A3
Fig. 10 Write Mode
Fig. 11 Read Mode
status
A2
A2
A1
A1
27
A0
A0
There are two methods in which JTAG can be used on the
GS1532:
(1) as a stand-alone JTAG interface to be used at in-circuit
(2) under control of the host for applications such as system
When the JTAG tests are applied by ATE, care must be
taken to disable any other devices driving the pins. If the
tests are to be applied only at ATE, this can be
accomplished with tri-state buffers used in conjunction with
the JTAG/HOST signal. This is shown in Figure 12.
t
4
D15
ATE (Automatic Test Equipment) during PCB assembly,
or
power on self tests.
D15
Application HOST
D14
D14
D13
D13
D12
t
5
D12
D11
D11
D10
D10
Fig. 12 In-Circuit JTAG
D9
D9
D8
D8
D7
D7
D6
In-circuit ATE probe
D6
D5
D5
D4
D4
D3
D2
D3
SCLK_TCK
SDIN_TDI
CS_TMS
SDOUT_TDO
JTAG_HOST
D1
D2
D0
D1
GS1532
D0
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