GS1560A Gennum Corporation, GS1560A Datasheet - Page 11

• Manufacturer Part Number: GS1560A
• Description: Reclocking Deserializer For HD-SDI, Sd-sdi & Dvb-asi With Loop Thru Cable Driver. 3.3/1.8V Supply.
• Manufacturer: Gennum Corporation

1.2 PIN DESCRIPTIONS (CONTINUED)
GENNUM CORPORATION
NUMBER
PIN DESCRIPTIONS (CONTINUED)
PIN DESCRIPTIONS (CONTINUED)
PIN DESCRIPTIONS (CONTINUED)
33, 68
37, 64
PIN
32
34
35
36
CORE_GND
CORE_VDD
FIFO_LD
NAME
H
F
V
Synchronous
Synchronous
Synchronous
Synchronous
with PCLK
with PCLK
with PCLK
with PCLK
TIMING
-
-
Output
Output
Output
Output
Power
Power
TYPE
11 of 55
CONTROL SIGNAL OUTPUT
Signal levels are LVCMOS/LVTTL compatible.
Used as a control signal for external FIFO(s).
Normally HIGH but will go LOW for one PCLK period at SAV.
Ground connection for the digital core logic. Connect to digital GND.
STATUS SIGNAL OUTPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to indicate the ODD / EVEN field of the video signal.
The F signal will be HIGH for the entire period of field 2 as indicated by the
F bit in the received TRS signals.
The F signal will be LOW for all lines in field 1 and for all lines in
progressive scan systems.
STATUS SIGNAL OUTPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to indicate the portion of the video field / frame that is used for
vertical blanking.
The V signal will be HIGH for the entire vertical blanking period as
indicated by the V bit in the received TRS signals.
The V signal will be LOW for all lines outside of the vertical blanking
interval.
STATUS SIGNAL OUTPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to indicate the portion of the video line containing active video data.
H signal timing is configurable via the H_CONFIG bit of the
IOPROC_DISABLE register accessible via the host interface.
Active Line Blanking (H_CONFIG = 0
The H signal will be HIGH for the entire horizontal blanking period,
including the EAV and SAV TRS words, and LOW otherwise. This is the
default setting.
TRS Based Blanking (H_CONFIG = 1
The H signal will be HIGH for the entire horizontal blanking period as
indicated by the H bit in the received TRS ID words, and LOW otherwise.
Power supply connection for the digital core logic. Connect to +1.8V DC
digital.
DESCRIPTION
h
h
)
)
27360-1