GS1560A Gennum Corporation, GS1560A Datasheet - Page 51

• Manufacturer Part Number: GS1560A
• Description: Reclocking Deserializer For HD-SDI, Sd-sdi & Dvb-asi With Loop Thru Cable Driver. 3.3/1.8V Supply.
• Manufacturer: Gennum Corporation

3.12.3 Configuration and Status Registers
Table 17 summarizes the GS1560A's internal status and
configuration registers.
All of these registers are available to the host via the GSPI
and are all individually addressable.
Where status registers contain less than the full 16 bits of
information however, two or more registers may be
combined at a single logical address.
Table 17: GS1560A internal registers
3.13 JTAG
3.13 JTAG
3.13 JTAG
3.13 JTAG
When the JTAG/HOST input pin of the GS1560A is set
HIGH, the host interface port will be configured for JTAG
test operation. In this mode, pins 27 through 30 become
TMS, TDO, TDI, and TCK. In addition, the RESET_TRST pin
will operate as the test reset pin.
Boundary scan testing using the JTAG interface will be
enabled in this mode.
There are two methods in which JTAG can be used on the
GS1560A:
1. As a stand-alone JTAG interface to be used at in-circuit
2. Under control of the host for applications such as
When the JTAG tests are applied by ATE, care must be
taken to disable any other devices driving the digital I/O
pins. If the tests are to be applied only at ATE, this can be
accomplished with tri-state buffers used in conjunction with
the JTAG/HOST input signal. This is shown in Figur 18.
GENNUM CORPORATION
005h - 009h
012h - 013h
014h - 017h
018h - 025h
ATE (Automatic Test Equipment) during PCB assembly;
or
system power on self tests.
ADDRESS
000h
001h
003h
004h
026h
REGISTER NAME
IOPROC_DISABLE
ERROR_STATUS
EDH_FLAG
VIDEO_STANDARD
ANC_TYPE
VIDEO_FORMAT
RASTER_STRUCTURE
EDH_CALC_RANGES
ERROR_MASK
SEE SECTION
3.10.2.1
3.10.5.2
3.10.6
3.10.5
3.10.7
3.10.4
3.10.3
3.10.4
3.10.5
51 of 55
Alternatively, if the test capabilities are to be used in the
system, the host may still cntrol the JTAG/HOST input
signal, but some means for tri-stating the host must exist in
order to use the interface at ATE. This is represented in
Figure 19.
Please contact your Gennum representative to obtain the
BSDL model for the GS1560A.
3.14 DEVICE POWER UP
3.14 DEVICE POWER UP
3.14 DEVICE POWER UP
3.14 DEVICE POWER UP
Because the GS1560A is designed to operate in a multi-volt
environment, any power up sequence is allowed. The
charge pump, phase detector, core logic, serial digital input
/ output buffers and digital I/O buffers should all be
powered up within 1ms of one another.
Device pins may also be driven prior to power up without
causing damage.
Application HOST
Tri-State
Application HOST
Fig. 18 In-Circuit JTAG
Fig. 19 System JTAG
In-circuit ATE probe
In-circuit ATE probe
SCLK_TCK
SDIN_TDI
CS_TMS
SDOUT_TDO
JTAG_HOST
CS_TMS
SCLK_TCK
SDIN_TDI
SDOUT_TDO
JTAG_HOST
GS1560A
GS1560A
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