GS1560A Gennum Corporation, GS1560A Datasheet - Page 15

• Manufacturer Part Number: GS1560A
• Description: Reclocking Deserializer For HD-SDI, Sd-sdi & Dvb-asi With Loop Thru Cable Driver. 3.3/1.8V Supply.
• Manufacturer: Gennum Corporation

1.2 PIN DESCRIPTIONS (CONTINUED)
GENNUM CORPORATION
NUMBER
PIN DESCRIPTIONS (CONTINUED)
PIN DESCRIPTIONS (CONTINUED)
PIN DESCRIPTIONS (CONTINUED)
PIN
70
71
72
MASTER/SLAVE
LOCKED
RC_BYP
NAME
Synchronous
Synchronous
Synchronous
with PCLK
TIMING
Non
Non
/Output
Output
TYPE
Input
Input
15 of 55
CONTROL SIGNAL INPUT / STATUS SIGNAL OUTPUT
Signal levels are LVCMOS/LVTTL compatible.
This pin will be an input set by the application layer in slave mode, and will
be an output set by the device in master mode.
Master Mode (MASTER/SLAVE = HIGH)
The RC_BYP signal will be HIGH only when the device has successfully
locked to a SMPTE or DVB-ASI compliant input data stream. In this case,
the serial digital loop-through output will be a reclocked version of the
input.
The RC_BYP signal will be LOW whenever the input does not conform to a
SMPTE or DVB-ASI compliant data stream. In this case, the serial digital
loop-through output will be a buffered version of the input.
Slave Mode (MASTER/SLAVE = LOW)
When set HIGH, the serial digital output will be a reclocked version of the
input signal regardless of whether the device is in SMPTE, DVB-ASI or
Data-Through mode.
When set LOW, the serial digital output will be a buffered version of the
input signal in all modes.
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to determine the input / output selection for the DVB_ASI, SD/HD,
RC_BYP and SMPTE_BYPASS pins.
When set HIGH, the GS1560A is set to operate in master mode where
DVB_ASI, SD/HD, RC_BYP and SMPTE_BYPASS become status signal
output pins set by the device. In this mode, the GS1560A will
automatically detect, reclock, deserialize and process SD SMPTE, HD
SMPTE, or DVB-ASI input data.
When set LOW, the GS1560A is set to operate in slave mode where
DVB_ASI,
signal input pins. In this mode, the application layer must set these
external device pins for the correct reception of either SMPTE or DVB-ASI
data. Slave mode also supports the reclocking and deserializing of data
not conforming to SMPTE or DVB-ASI streams.
STATUS SIGNAL OUTPUT
Signal levels are LVCMOS / LVTTL compatible.
The LOCKED signal will be HIGH whenever the device has correctly
received and locked to SMPTE compliant data in SMPTE mode or DVB-
ASI compliant data in DVB-ASI mode, or when the reclocker has achieved
lock in Data-Through mode.
It will be LOW otherwise.
SD/HD, RC_BYP and SMPTE_BYPASS become control
DESCRIPTION
27360-1