GS1560A Gennum Corporation, GS1560A Datasheet - Page 43

• Manufacturer Part Number: GS1560A
• Description: Reclocking Deserializer For HD-SDI, Sd-sdi & Dvb-asi With Loop Thru Cable Driver. 3.3/1.8V Supply.
• Manufacturer: Gennum Corporation

Table 12: Host Interface Description for Error Mask Register
3.10.5.1 Video Standard Error Detection
If a mismatch between the received SMPTE 352M packets
and the calculated video standard occurs, the GS1560A will
indicate a video standard error by setting the VD_STD_ERR
bit of the ERROR_STATUS register HIGH.
3.10.5.2 EDH CRC Error Detection
The GS1560A calculates Full Field (FF) and Active Picture
(AP) CRC words according to SMPTE RP165 in support of
Error Detection and Handling packets in SD signals.
These calculated CRC values are compared with the
received CRC values. If a mismatch is detected, the error is
flagged in the AP_CRC_ERR and/or FF_CRC_ERR bits of
the ERROR_STATUS register. These two flags are shared
between fields 1 and 2.
The AP_CRC_ERR bit will be set HIGH when an active
picture CRC mismatch has been detected in field 1 or 2.
The FF_CRC_ERR bit will be set HIGH when a full field CRC
mismatch has been detected in field 1 or 2.
EDH CRC errors will only be indicated when the device is
operating in SD mode (SD/HD = HIGH), and when the
device has correctly received EDH packets.
GENNUM CORPORATION
REGISTER NAME
ERROR_MASK
Address: 026h
15-11
BIT
10
9
8
7
6
5
4
3
2
1
0
AP_CRC_ERR_MASK
VD_STD_ERR_MASK
FF_CRC_ERR_MASK
CCRC_ERR_MASK
LNUM_ERR_MASK
LOCK_ERR_MASK
YCRC_ERR_MASK
CCS_ERR_MASK
YCS_ERR_MASK
SAV_ERR_MASK
EAV_ERR_MASK
NAME
Video Standard Error Flag Mask bit.
Full Field CRC Error Flag Mask bit.
Active Picture CRC Error Flag Mask bit.
Lock Error Flag Mask bit.
Chroma Checksum Error Flag Mask bit.
Luma Checksum Error Flag Mask bit.
Chroma CRC Error Flag Mask bit.
Luma CRC Error Flag Mask bit.
Line Number Error Flag Mask bit.
Start of Active Video Error Flag Mask bit.
End of Active Video Error Flag Mask bit.
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SMPTE RP165 specifies the calculation ranges and scope
of EDH data for standard 525 and 625 component digital
interfaces. The GS1560A will utilize these standard ranges
by default.
If the received video format does not correspond to 525 or
625 digital component video standards as determined by
the flywheel pixel and line counters, then one of two
schemes for determining the EDH calculation ranges will be
employed:
1. Ranges will be based on the line and pixel ranges
2. In the absence of user-programmed calculation ranges,
The
programming EDH calculation ranges include active picture
and full field line/pixel start and end positions for both
fields. Table 13 shows the relevant registers, which default
to '0' after device reset or power up.
If any or all of these register values are zero, then the EDH
CRC calculation ranges will be determined from the
flywheel generated H signal. The first active and full field
pixel will always be the first pixel after the SAV TRS code
word. The last active and full field pixel will always be the
last pixel before the start of the EAV TRS code words.
programmed by the host interface; or
ranges will be determined from the received TRS timing
information.
registers
Not Used
DESCRIPTION
available
to
the
host
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
interface
DEFAULT
0
0
0
0
0
0
0
0
0
0
0
27360-1
for