GS1560A Gennum Corporation, GS1560A Datasheet - Page 35

• Manufacturer Part Number: GS1560A
• Description: Reclocking Deserializer For HD-SDI, Sd-sdi & Dvb-asi With Loop Thru Cable Driver. 3.3/1.8V Supply.
• Manufacturer: Gennum Corporation

The FIFO load pulse will be generated such that it is co-
timed to the SAV XYZ code word presented to the output
data bus. This ensures that the next PCLK cycle will
correspond to the first active sample of the video line.
3.10.2 Ancillary Data Detection and Indication
The GS1560A will detect all types of ancillary data in either
the vertical or horizontal blanking spaces and indicate via
the status signal output pins YANC and CANC the position
of ancillary data in the output data stream. These status
signal outputs are synchronous with PCLK and can be used
as clock enables to external logic, or as write enables to an
external FIFO or other memory device.
When operating in HD mode, (SD/HD = LOW), the YANC
signal will be HIGH whenever ancillary data is detected in
the luma data stream, and the CANC signal will be HIGH
whenever ancillary data is detected in the chroma data
stream.
GENNUM CORPORATION
Y/Cr/Cb DATA OUT
MULTIPLEXED
FIFO_LD
PCLK
CHROMA DATA OUT
LUMA DATA OUT
3FF
Y/Cr/Cb DATA OUT
FIFO_LD
MULTIPLEXED
PCLK
CHROMA DATA OUT
FIFO_LD
PCLK
LUMA DATA OUT
3FF
FIFO_LD
PCLK
Fig. 10a HD FIFO_LD Pulse Timing
Fig. 10b SD FIFO_LD Pulse Timing
FIFO LOAD PULSE - HD 20BIT OUTPUT MODE
FIFO LOAD PULSE - HD 10BIT OUTPUT MODE
3FF
3FF
000
3FF
FIFO LOAD PULSE - SD 10BIT OUTPUT MODE
FIFO LOAD PULSE - SD 20BIT OUTPUT MODE
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000
3FF
000
000
000
000
Figures 10a,b show the timing relationship between the
FIFO_LD signal and the output video data.
In SD mode, (SD/HD = HIGH), the YANC and CANC signal
operation will depend on the output data format. For 20-bit
demultiplexed data, (see section 3.11), the YANC and
CANC signals will operate independently. However, for 10-
bit multiplexed data, the YANC and CANC signals will both
be HIGH whenever ancillary data is detected.
The signals will be HIGH from the start of the ancillary data
preamble and will remain HIGH until after the ancillary data
checksum.
The operation of the YANC and CANC signals is shown in
Figures 11a,b.
(SAV)
XYZ
000
000
000
000
000
(SAV)
(SAV)
(SAV)
XYZ
XYZ
XYZ
000
(SAV)
XYZ
(SAV)
XYZ
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