S3042 AMCC (Applied Micro Circuits Corp), S3042 Datasheet
S3042
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S3042 Summary of contents
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DEVICE SPECIFICATION SONET/SDH/ATM OC-48 16:1 TRANSMITTER BiCMOS LVPECL CLOCK GENERATOR SONET/SDH/ATM OC-48 16:1 TRANSMITTER SONET/SDH/ATM OC-12 TRANSMITTER AND RECEIVER FEATURES • Micro-power Bipolar supply • Complies with Bellcore, and ITU-T specifications • On-chip high-frequency PLL for clock generation • Supports ...
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S3043 SONET OVERVIEW Synchronous Optical Network (SONET standard for connecting one fiber system to another at the opti- cal level. SONET, together with the Synchronous Digital Hierarchy (SDH) administered by the ITU-T, forms a single international standard for ...
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SONET/SDH/ATM OC-48 16:1 TRANSMITTER S3043 OVERVIEW The S3043 transmitter implements SONET/SDH se- rialization and transmission functions. The block dia- gram in Figure 4 shows the basic operation of the chip. This chip can be used to implement the front end ...
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S3043 S3043 ARCHITECTURE/FUNCTIONAL DESIGN MUX OPERATION The S3043 performs the serializing stage in the pro- cessing of a transmit SONET STS-48 bit serial data stream. It converts the byte serial 155.52 Mbyte/sec data stream to bit serial format at 2.488 ...
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SONET/SDH/ATM OC-48 16:1 TRANSMITTER Table 3. Input Pin Assignment and Descriptions ...
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S3043 Table 3. Input Pin Assignment and Descriptions (Continued ...
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SONET/SDH/ATM OC-48 16:1 TRANSMITTER Table 4. Output Pin Assignment and Descriptions ...
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S3043 Table 5. Common Pin Assignment and Description ...
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SONET/SDH/ATM OC-48 16:1 TRANSMITTER Figure 5. S3043 Pinout LSCLKP 1 LSCLKN 2 LVPECLVCC 3 LVPECLGND 4 LLEB 5 LSDP 6 LSDN 7 DLEB 8 RSTB 9 LVPECLGND 10 LLCLKP 11 LLCLKN 12 TESTEN 13 LLDP 14 LLDN 15 16 LVPECLVCC ...
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S3043 Figure 6. 80 PQFP/TEP Package TOP VIEW Note: The S3043 package is equipped with an embedded conductive heatsink on the bottom (board side). Active circuitry and vias should not appear in the area immediately under the package. This heatsink ...
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SONET/SDH/ATM OC-48 16:1 TRANSMITTER Table 7. Performance Specifications ...
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S3043 Table 10. Power Consumption Add 70 mA for loopback active. Table 11. LVTTL Input/Output DC Characteristics ...
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SONET/SDH/ATM OC-48 16:1 TRANSMITTER Table 14. Internally Biased Differential LVPECL Input DC Characteristics ...
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S3043 Table 18. Differential LVPECL Input DC Characteristics ...
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SONET/SDH/ATM OC-48 16:1 TRANSMITTER Figure 7. Line Loopback Input Timing Diagram LLCLKP LLDP/N Notes on High-Speed LVPECL Input Timing: 1. Timing is measured from the cross-over point of the reference signal to the cross-over point of the input. Table 20. ...
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S3043 Figure 8. External Loop Filter Figure 9. CML Output to +5V PECL Input AC Coupled Termination +3.3V S3043 TSDP/N TSCLKP/N Figure 10. -5V Single Ended ECL Driver to S3043 Input AC Coupled Termination -5.2V ECL 16 SONET/SDH/ATM OC-48 16:1 ...
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SONET/SDH/ATM OC-48 16:1 TRANSMITTER Figure 11. +5V Differential PECL Driver to S3043 Input AC Coupled Termination +5V 330 330 Figure 12. S3043 to S3043 Terminations +3.3V S3043 PCLKP/N August 10, 1999 / Revision E 3.3V 0.01 F Zo=50 82 3.3V ...
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S3043 Figure 13. Single-Ended PECL Output Termination +3.3V S3043 PULSE Figure 14. S3043 to S3044 for Diagnostic Loopback +3.3V S3043 LSDP/N LSCLKP/N Figure 15. Single-Ended LVPECL Driver to S3043 Input AC Coupled Termination Single-Ended Driver 18 SONET/SDH/ATM OC-48 16:1 TRANSMITTER ...
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SONET/SDH/ATM OC-48 16:1 TRANSMITTER Figure 16. AC Input Timing PICLKP PIN[15:0] 1. When a set-up time is specified on LVPECL signals between an input and a clock, the set-up time is the time in picoseconds from the 50% point of ...
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S3043 The S3043 utilizes a unique elastic store buffer which can be set in two different configurations allowing the system designer to be flexible in the way a system layed out. The configuration of the elastic store ...
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APPLICATION NOTE SONET/SDH/ATM OC-48 16:1 TRANSMITTER Figure 20. PCLK PICLK PIN[15:0] VALID DATA 1 PULSE READ DON’T CARE August 10, 1999 / Revision E tH PIN tS PIN VALID DATA 3 VALID DATA 2 tS PIN tH PIN S3043 VALID ...
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S3043 In the figure shown below, we are using the 2nd configuration of the elastic store buffer. This configuration fully utilizes the elastic store buffer and allows the user a delay accommodation ns. The PULSE delay ...
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APPLICATION NOTE SONET/SDH/ATM OC-48 16:1 TRANSMITTER Figure 22. PCLK tP PICLK PICLK tS PULSE tH PULSE PULSE tP PRCLK tS PIN READ tS PIN PIN[15:0] VALID DATA 1 August 10, 1999 / Revision E tH PIN tH PIN VALID DATA ...
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S3043 Figure 23. OSCILLATOR CUSTOMER LOGIC In some applications it is necessary to "forward clock" the data in a SONET/SDH system. In this application the reference clock from which the high speed serial clock is synthesized and the parallel data ...
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SONET/SDH/ATM OC-48 16:1 TRANSMITTER Ordering Information – 6290 Sequence Drive, San Diego, CA 92121 Phone: (858) ...