S3042 AMCC (Applied Micro Circuits Corp), S3042 Datasheet - Page 20

• Manufacturer Part Number: S3042
• Description: Sonet/sdh/atm OC-48 1:8 Receiver
• Manufacturer: AMCC (Applied Micro Circuits Corp)

Figure 19. Block Diagram
Block Diagram
In the configuration shown above, both the loops (PCLK to PICLK) and (Pulse to Read) have 0 delay (they are
shorted). S3043 is clocking data out of the customer logic. The oscillator frequency REFCLK is given to the PLL.
The output of the PLL is given to the multiplier and divider circuits. The output of the chip PCLK, is used to clock
data out of the customer logic. The PICLK is in phase and has the same frequency as PCLK. It is used to clock
data into the register in the S3043. The data will have the same frequency as PICLK, but it may not be in phase
with PICLK. It is important to meet the set-up and hold time constraints in this case.
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The S3043 utilizes a unique elastic store buffer which can be set in two different configurations allowing the
system designer to be flexible in the way a system is to be layed out. The configuration of the elastic store buffer
is dependent upon the I/O pins which comprise the Synch Timing loop. This loop is formed from PULSE(I/P) to
READ(O/P) and PCLK(I/P) to PICLK(O/P). The elastic store buffer can be thought of as a memory stack with a
read pointer. The PULSE signal is the read pointer which announces that it has read a register and when fed
back to READ input, it synchronizes the write operation of the buffer so as not to simultaneously write over the
same register that it has read previously.
S3043
CUSTOMER LOGIC
16
SONET/SDH/ATM OC-48 16:1 TRANSMITTER
PICLK P/N
PIN[15:0]
PCLK P/N
Pulse
REFCLK P/N
S3043
DIV
FIFO
OSCILLATOR
Read
PLL
August 10, 1999 / Revision E
APPLICATION NOTE