S3043 AMCC (Applied Micro Circuits Corp), S3043 Datasheet
S3043
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S3043 Summary of contents
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... The low jitter LVPECL interface guarantees compli- ance with the bit-error rate requirements of the Bellcore and ITU-T standards. The S3044 is pack- aged PQFP/TEP, offering designers a small package outline. OTX ORX S3040 ORX S3044 16 S3040 Rx 16 S3043 OTX Tx ® S3044 S3044 S3044 1 ...
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... Details of data timing can be seen in Figures 7 through 9. Internal clocking and control functions are transparent to the user. Suggested Interface Devices AMCC AMCC 1:16 SERIAL TO PARALLEL S3040 Clock Recovery Device S3043 OC-48 Transmitter 16 POUT[15: RX155MCKP/N TIMING 2 GEN POCLKP/N FRAME BYTE 1 DETECT FP ...
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SONET/SDH/ATM OC-48 1:16 RECEIVER SONET OVERVIEW Synchronous Optical Network (SONET standard for connecting one fiber system to another at the opti- cal level. SONET, together with the Synchronous Digital Hierarchy (SDH) administered by the ITU-T, forms a single ...
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S3044 RECEIVER OPERATION The S3044 receiver chip provides the first stage of digital processing of a receive SONET STS-48 bit- serial stream. It converts the bit-serial 2.488 Gbps data stream into a 155.52 Mbyte/sec byte-serial data format. A loopback mode ...
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SONET/SDH/ATM OC-48 1:16 RECEIVER Table 2. Input Pin Assignment and Description ...
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S3044 Table 3. Output Pin Assignment and Description ...
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SONET/SDH/ATM OC-48 1:16 RECEIVER Table 4. Common Pin Assignment and Description ...
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S3044 Figure 5. S3044 Pinout LVPECLVCC 1 LVPECLGND 2 RSDP 3 RSDN 4 LVPECLVCC 5 LVPECLGND 6 RSCLKP 7 RSCLKN 8 COREVCC 9 COREGND 10 COREVCC 11 COREGND 12 COREVCC 13 COREGND 14 LVTTLVCC 15 16 OOF FRAMEN 17 KILLRXCLK ...
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SONET/SDH/ATM OC-48 1:16 RECEIVER Figure 6. 80 PQFP/TEP Package TOP VIEW Note: The S3044 package is equipped with an embedded conductive heatsink on the bottom (board side). Active circuitry and vias should not appear in the area immediately under the ...
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S3044 Table 6. Low Swing Differential CML Output DC Characteristics ...
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SONET/SDH/ATM OC-48 1:16 RECEIVER Table 10. Single Ended LVPECL Output DC Characteristics ...
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S3044 Table 13. LVTTL Input/Output DC Characteristics ...
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SONET/SDH/ATM OC-48 1:16 RECEIVER Table 14. Absolute Maximum Ratings ...
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S3044 Table 17. AC Receiver Timing Characteristics ...
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SONET/SDH/ATM OC-48 1:16 RECEIVER RECEIVER FRAMING Figure 10 shows a typical reframe sequence in which a byte realignment is made. The frame and byte boundary detection is enabled by the rising edge of OOF. Both boundaries are recognized upon receipt ...
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S3044 Figure 11. OOF Timing (FRAMEN = 1) OOF FP SEARCH Figure 12. FRAMEN Timing OOF FRAMEN FP SEARCH Figure 13. Differential Voltage Measurement 16 SONET/SDH/ATM OC-48 1:16 RECEIVER BOUNDARY DETECTION ENABLED BOUNDARY DETECTION ENABLED Single-ended V SINGLE swing V ...
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... SONET/SDH/ATM OC-48 1:16 RECEIVER Figure 14. +5V Differential PECL Driver to S3044 Input AC Coupled Termination +5V 330 Figure 15. S3040 to S3042/S3044 Terminations S3040 SERDATOP/N SERCLKOP/N Figure 16. S3044 to S3043 Terminations S3044 LLCLKP/N LLDP/N November 22, 1999 / Revision F Vcc -0.70V (DC AVG) . =50 0 330 Z =50 . Vcc -0.70V (DC AVG) S3042/44 ...
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S3044 Figure 17. Single-Ended PECL Output Termination +3.3V S3044 POUTP Figure 18. Alternative Single-Ended PECL Output Termination S3044 Figure 19. Single-Ended PECL Output Termination S3044 18 SONET/SDH/ATM OC-48 1:16 RECEIVER Vcc Z = 220 130 +3.3V Z =50 ...
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... SONET/SDH/ATM OC-48 1:16 RECEIVER Figure 20. S3043 to S3044 for Diagnostic Loopback Figure 21. Single-Ended LVPECL Driver to S3044 Input AC Coupled Termination Single-Ended Driver Figure 22. Differential LVPECL Termination POCLKP/N November 22, 1999 / Revision F +3. =50 0 S3043 LSDP/N LSCLKP/N Vcc Vcc -0.70V (DC AVG) . =50 0 300 .01 F Vcc -0.70V (DC AVG) +3 ...
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S3044 S3044 Ordering Information – 6290 Sequence Drive, San Diego, CA 92121 Phone: (858) 450-9333 • ...