S3057 AMCC (Applied Micro Circuits Corp), S3057 Datasheet - Page 4

• Manufacturer Part Number: S3057
• Description: Bicmos Lvpecl Clock Generator Sonet/sdh/atm Oc-12 Transmitter And Receiver Multirate (oc-48/24/12/3/gbe) Sonet/sdh/atm Transceiver
• Manufacturer: AMCC (Applied Micro Circuits Corp)

S3063 ARCHITECTURE/FUNCTIONAL
DESIGN
MUX OPERATION
The S3063 performs the serializing stage in the pro-
cessing of a transmit SONET STS-48 bit serial data
stream. It converts the 16-bit serial 155.52 Mbyte/sec
data stream to bit serial format at 2.488 Gbps. Diag-
nostic loopback is provided (transmitter to receiver),
and line loopback is also provided (receiver to trans-
mitter).
A high-frequency bit clock is generated from a
155.52 MHz frequency reference by using a fre-
quency synthesizer consisting of an on-chip phase-
locked loop circuit with a divider, VCO and loop filter.
Clock Divider and Phase Detector
The clock divider and phase detector, shown in the
block diagram in Figure 4, contains monolithic PLL
components that generate signals required to drive
the loop filter.
The REFCLK input must be generated from a differ-
ential LVPECL crystal oscillator which has a fre-
quency accuracy which exceeds the value stated in
Table 6 in order for the VCOCLK frequency to have
the same accuracy required for operation in a
SONET system.
In order to meet the 0.01 UI SONET jitter generation,
the maximum reference clock jitter must be guaran-
teed over the 12 kHz to 20 MHz bandwidth. For
details of reference clock jitter requirements, see
Table 2.
The on–chip phase detector, which compares the
phase relationship between the VCO input and the
REFCLKP/N input, drives the loop filter.
Timing Generator
The timing generator function, seen in Figure 4, pro-
vides two separate functions. It provides a 16-bit par-
allel rate version of the TSCLK, and a mechanism for
aligning the phase between the incoming 16-bit paral-
Table 2. Reference Jitter Limits
4
S3063
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SONET/SDH/ATM OC-48 DIFFERENTIAL 16:1 TRANSMITTER
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lel clock and the clock which loads the parallel-to-
serial shift register.
The PCLK output is a 16-bit parallel rate version of
TSCLK. For STS-48, the PCLK frequency is 155.52
MHz. PCLK is intended for use as a 16-bit rate clock
for upstream multiplexing and overhead processing
circuits. Using PCLK for upstream circuits will ensure
a stable frequency and phase relationship between
the data coming into and leaving the S3063 device.
In the parallel-to-serial conversion process, the in-
coming data is passed from the PICLK 16-bit parallel
clock timing domain to the internally generated 16-bit
parallel clock timing domain, which is phase aligned
to TSCLK.
The timing generator also produces a feedback ref-
erence clock to the phase detector. A counter divides
the synthesized clock down to the same frequency
as the Reference Clock.
Parallel-to-Serial Converter
The parallel-to-serial converter shown in Figure 4 is
comprised of a FIFO and a parallel-to-serial register.
The FIFO input latches the data from the PINP/N[15:0]
bus on the rising edge of PICLKP. The parallel-to-serial
register is a loadable shift register which takes its paral-
lel input from the FIFO output.
An internally generated divide by 16 clock, which is
phase aligned to the transmit serial clock as de-
scribed in the Timing Generator description, activates
the parallel data transfer between registers. The serial
data is shifted out of the parallel-to-serial register at
the TSCLK rate.
FIFO
A FIFO is added to decouple the internal and exter-
nal (PICLK) clocks. The internally generated divide
by 16 clock is used to clock out data from the FIFO.
PHINIT and LOCKDET are used to center or reset
the FIFO. The PHINIT and LOCKDET signals will
center the FIFO after the third PICLK pulse. This is
in order to insure that PICLK is stable. This scheme
allows the user to have an infinite PCLK to PICLK
delay through the ASIC. Once the FIFO is centered,
the PCLK to PICLK delay can have a maximum drift
as specified in Table 20.
December 6, 1999 / Revision NC