S3057 AMCC (Applied Micro Circuits Corp), S3057 Datasheet - Page 5

• Manufacturer Part Number: S3057
• Description: Bicmos Lvpecl Clock Generator Sonet/sdh/atm Oc-12 Transmitter And Receiver Multirate (oc-48/24/12/3/gbe) Sonet/sdh/atm Transceiver
• Manufacturer: AMCC (Applied Micro Circuits Corp)

FIFO Initialization
The FIFO can be initialized in one of the following
three ways:
1. During power up, once the PLL has locked to the
2. When RSTB goes active, the entire chip is reset.
3. The user can also initialize the FIFO by raising
During normal running operation, the incoming data
is passed from the PICLK timing domain to the inter-
nally generated divide by 16 clock timing domain.
Although the frequency of PICLK and the internally
generated clock is the same, their phase relationship
is arbitrary. To prevent errors caused by short setup
or hold times between the two timing domains, the
timing generator circuitry monitors the phase rela-
tionship between PICLK and the internally generated
clock. When a potential setup or hold time violation
is detected, the phase error goes high. If the condi-
tion persists, PHERR will remain high. When
PHERR conditions occur, PHINIT should be acti-
vated to recenter the FIFO (at least 2 PCLK peri-
ods). This can be done by connecting PHERR to
PHINIT. When realignment occurs up to ten bytes of
data will be lost. The user can also take in the
PHERR signal, process it and send an output to
PHINIT in such a way that idle bytes are lost during
the realignment process. PHERR will go inactive
when the realignment is complete. (See Figure 11).
December 6, 1999 / Revision NC
SONET/SDH/ATM OC-48 DIFFERENTIAL 16:1 TRANSMITTER
reference clock provided on the REFCLK pins, the
LOCKDET will go active and initialize the FIFO.
This causes the PLL to go out of lock and thus the
LOCKDET goes inactive. When the PLL reac-
quires the lock, the LOCKDET goes active and
initializes the FIFO. Note: PCLK is held reset
when RSTB is active.
PHINIT.
OTHER OPERATING MODES
Diagnostic Loopback
When the Diagnostic Loopback Enable (DLEB) input
is active, a loopback from the transmitter to the re-
ceiver at the serial data rate can be set up for diag-
nostic purposes. The differential serial output clock
and data from the transmitter (LSCLK and LSD) is
routed to the serial-to-parallel block in place of the
normal data stream (RSCLK and RSD).
Line Loopback
The line loopback circuitry consists of alternate clock
and data output drivers. For the S3063, it selects the
source of the data and clock which is output on TSD
and TSCLK. When the Line Loopback Enable
(LLEB) input is inactive, it selects data and clock
from the parallel to serial converter block. When
LLEB is active, it forces the output data multiplexer
to select data and clock from the LLD and LLCLK
inputs, and a receive-to-transmit loopback can be
established at the serial data rate. The LLEB and
DLEB can be active at the same time.
S3063
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