S3059 AMCC (Applied Micro Circuits Corp), S3059 Datasheet - Page 5

• Manufacturer Part Number: S3059
• Description: Multi-rate (OC-48/24/12/3/GBE) Sonet/sdh/atm Transceiver
• Manufacturer: AMCC (Applied Micro Circuits Corp)

Parallel-to-Serial Converter
The parallel-to-serial converter shown in Figure 2 is
comprised of a FIFO and a parallel-to-serial register.
The FIFO input latches the data from the PINP/N[15:0]
bus on the rising edge of PICLK. The parallel-to-serial
register is a loadable shift register which takes its paral-
lel input from the FIFO output.
An internally generated divide by 16 clock, which is
phase aligned to the transmit serial clock as de-
scribed in the timing generator description, activates
the parallel data transfer between registers. The serial
data is shifted out of the parallel-to-serial register at
the TSCLK rate.
FIFO
A FIFO is added to decouple the internal and exter-
nal (PICLK) clocks. The internally generated divide
by 16 clock is used to clock out data from the FIFO.
Phase Initialization (PHINIT) and Lock Detect
(LOCKDET) are used to center or reset the FIFO.
The PHINIT and LOCKDET signals will center the
FIFO after the third PICLK pulse. This is in order to
insure that PICLK is stable. This scheme allows the
user to have an infinite PCLK to PICLK delay
through the ASIC. Once the FIFO is centered, the
PCLK to PICLK delay can have a maximum drift
specified by Table 18.
FIFO Initialization
The FIFO can be initialized in one of the following
three ways:
1. During power up, once the PLL has locked to the
2. When RSTB goes active, the entire chip is reset.
3. The user can also initialize the FIFO by raising
During the normal running operation, the incoming
data is passed from the PICLK timing domain to the
internally generated divide by 16 clock timing do-
main. Although the frequency of PICLK and the
October 31, 2000 / Revision B
MULTI-RATE (OC-48/24/12/3/GBE) SONET/SDH/ATM TRANSCEIVER
reference clock provided on the REFCLK pins, the
LOCKDET will go active and initialize the FIFO.
This causes the PLL to go out of lock and thus the
LOCKDET goes inactive. When the PLL reac-
quires the lock, the LOCKDET goes active and
initializes the FIFO. Note: PCLK is held reset
when RSTB is active.
PHINIT.
internally generated clock is the same, their phase
relationship is arbitrary. To prevent errors caused by
short setup or hold times between the two timing
domains, the timing generator circuitry monitors the
phase relationship between PICLK and the internally
generated clock. When a potential setup or hold time
violation is detected, the phase error goes High.
When PHERR conditions occur, PHINIT should be
activated to recenter the FIFO (at least 2 PCLK peri-
ods). This can be done by connecting PHERR to
PHINIT. When realignment occurs up to 10 bytes of
data will be lost. The user can also take in the
PHERR signal, process it and send an output to
PHINIT in such a way that idle bytes are lost during
the realignment process. PHERR will go inactive
when the realignment is complete.
RECEIVER OPERATION
The S3059 receiver chip provides the first stage of
the digital processing of a receive SONET STS-48/
STS-24/STS-12/STS-3/GBE bit-serial stream. It con-
verts the bit-serial 2.488 Gbps, 1.244 Gbps, 622.08
Mbps, 155.52 Mbps, 1.25 Gbps data stream into a
16-bit parallel data format. A loopback mode is pro-
vided for diagnostic loopback (transmitter to
receiver). A line loopback (receiver to transmitter) is
also provided. Both line and local loopback modes
can be active at the same time.
Serial-to-Parallel Converter
The serial-to-parallel converter consists of two 16-bit
registers. The first is a serial-in, parallel-out shift reg-
ister, which performs the serial-to-parallel conversion
clocked by the clock recovery block. On the falling
edge of the POCLK, the data in the parallel register
is transferred to an output parallel register which
drives POUTP/N[15:0].
OTHER OPERATING MODES
Diagnostic Loopback
When the Diagnostic Loopback Enable (DLEB) input
is active, a loopback from the transmitter to the re-
ceiver at the serial data rate can be set up for
diagnostic purposes. The differential serial output
data from the transmitter is routed to the serial-to-
parallel block in place of the normal Receive Serial
Data (RSD). TSD/TSCLK outputs are active. DLEB
takes precedence over SDLVPECL and SDLVTTL.
S3059
5