S3059 AMCC (Applied Micro Circuits Corp), S3059 Datasheet - Page 6

• Manufacturer Part Number: S3059
• Description: Multi-rate (OC-48/24/12/3/GBE) Sonet/sdh/atm Transceiver
• Manufacturer: AMCC (Applied Micro Circuits Corp)

Line Loopback
The line loopback circuitry selects the source of the
data and clock which is output on TSD and TSCLK.
When the Line Loopback Enable (LLEB) input is in-
active, it selects data and clock from the parallel to
serial converter block. When LLEB is active, it forces
the output data multiplexer to select data and clock
from the RSD and RSCLK inputs, and a receive-to-
transmit loopback can be established at the serial
data rate. Diagnostic loopback and line loopback can
be active at the same time.
Loop Timing
In Serial Loop Timing (SLPTIME) mode, the clock
synthesizer PLL of the S3059 is bypassed, and the
timing of the entire transmitter section is controlled
by the Receive Serial Clock (RSCLKP/N). This mode
is entered by setting the SLPTIME input to an LVTTL
high level.
In this mode the REFCLKP/N input is not used. It
should be carefully noted that the internal PLL con-
tinues to operate in this mode, and continues as the
source for the 19MCK and 155MCKP/N, and if these
signals are being used (e.g. as the reference for an
external S3056 clock recovery device), the
REFCLKP/N inputs must be properly driven.
In Reference Loop Timing (RLPTIME) mode, the
parallel clock from the receiver (POCLK) is used as
the reference clock to the transmitter. In this mode,
the REFCLKP/N input is not used. The 19MCK and
155MCKP/N are generated from the POCLK in this
operating mode. When operating the S3059 in
RLPTIME mode, the 19MCK and 155MCKP/N out-
puts should not be used as the back-up reference
clock for a clock and data recovery device (S3056,
S3040). When performing loopback testing (DLEB),
the S3059 must not be in RLPTIME.
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S3059
MULTI-RATE (OC-48/24/12/3/GBE) SONET/SDH/ATM TRANSCEIVER
“Squelched Clock” Operation
Some integrated optical receiver/clock recovery
modules force their recovered serial receive clock
output to the logic zero state if the optical signal is
removed or reduced below a fixed threshold. This
condition is accompanied by the expected
deassertion of the signal detect output.
The S3059 has been designed for operation with
clock recovery devices that provide a continuous se-
rial clock for seamless downstream clocking in the
event of optical signal loss.
For operation with an optical transceiver that pro-
vides the “squelched clock” behavior as described
above, the S3059 can be operated in the “squelched
clock” mode by activating the SQUELCH pin.
In this condition, the RSCLKP/N is used for all re-
ceiver timing when the SDLVPECL/SDLVTTL inputs
are in the active state. When the SDLVPECL/
SDLVTTL inputs are placed in the inactive state (usu-
ally by the deassertion of LOCKDET or signal detect
from the optical transceiver/clock recovery unit) the
transmitter serial clock will be used to maintain timing
in the receiver section. This will allow the POCLK to
continue to run and the parallel outputs to flush out
the last received characters and then assume the all
zero state imposed at the serial data input.
It is important to note that in this mode there will be
a one time shortening or lengthening of the POCLK
cycle, resulting in an apparent phase shift in the
POCLK at the deassertion of the SD condition. An-
other similar phase shift will occur when the SD
condition is reasserted.
In the normal operating mode with SQUELCH inac-
tive, there will be no phase discontinuities at the
POCLK output during signal loss or reacquisition
(assuming operation with continuous clocking from
the CRU device such as the AMCC S3040, S3050,
or S3056).
October 31, 2000 / Revision B