S3064 AMCC (Applied Micro Circuits Corp), S3064 Datasheet

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S3064

Manufacturer Part Number
S3064
Description
Bicmos Lvpecl Clock Generator Sonet/sdh/atm Oc-12 Transmitter And Receiver Sonet/sdh/atm Oc-48 Differential 1:16 Receiver
Manufacturer
AMCC (Applied Micro Circuits Corp)
Datasheet
1.S3064.pdf (23 pages)
FEATURES
APPLICATIONS
Figure 1. System Block Diagram
August 27, 1999 / Revision B
DEVICE
SPECIFICATION
SONET/SDH/ATM OC-12 TRANSMITTER AND RECEIVER
SONET/SDH/ATM OC-48 16:1 TRANSMITTER
BiCMOS LVPECL CLOCK GENERATOR
SONET/SDH/ATM OC-48 16:1 TRANSMITTER
• Micro-power Bipolar supply
• Complies with Bellcore and ITU-T
• On-chip high-frequency PLL for clock
• Supports 2.488 Gbps (OC-48)
• Reference frequency of 155.52 MHz
• Interface to both LVPECL and LVTTL logic
• 16-bit LVPECL data path
• Compact 80 PQFP/TEP package
• Diagnostic loopback mode
• Line loopback
• Lock detect
• Low jitter LVPECL interface
• Internal FIFO to decouple transmit clocks
• Single 3.3V supply
• SONET/SDH-based transmission systems
• SONET/SDH modules
• SONET/SDH test equipment
• ATM over SONET/SDH
• DWDM Systems
• Section repeaters
• Add Drop Multiplexers (ADM)
• Broad-band cross-connects
• Fiber optic terminators
• Fiber optic test equipment
specifications
generation
16
16
S3083
S3044
Tx
Rx
S3040
OTX
ORX
ORX
GENERAL DESCRIPTION
The S3083 SONET/SDH MUX chip is a fully integrated
serialization SONET OC-48 (2.488 Gbps) interface de-
vice. The chip performs all necessary parallel-to-serial
functions in conformance with SONET/SDH transmis-
sion standards. The device is suitable for SONET-
based ATM applications. Figure 1 shows a typical
network application.
On-chip clock synthesis PLL components are con-
tained in the S3083 MUX chip allowing the use of a
slower external transmit clock reference. The chip
can be used with 155.52 MHz reference clock, in
support of existing system clocking schemes.
The low jitter LVPECL interface guarantees compli-
ance with the bit-error rate requirements of the
Bellcore and ITU-T standards. The S3083 is pack-
aged in a 80 PQFP/TEP, offering designers a small
package outline.
OTX
S3040
S3044
S3083
Rx
Tx
16
16
S3083
S3083
S3083
®
1

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S3064 Summary of contents

Page 1

DEVICE SPECIFICATION SONET/SDH/ATM OC-48 16:1 TRANSMITTER BiCMOS LVPECL CLOCK GENERATOR SONET/SDH/ATM OC-48 16:1 TRANSMITTER SONET/SDH/ATM OC-12 TRANSMITTER AND RECEIVER FEATURES • Micro-power Bipolar supply • Complies with Bellcore and ITU-T specifications • On-chip high-frequency PLL for clock generation • Supports ...

Page 2

S3083 SONET OVERVIEW Synchronous Optical Network (SONET standard for connecting one fiber system to another at the opti- cal level. SONET, together with the Synchronous Digital Hierarchy (SDH) administered by the ITU-T, forms a single international standard for ...

Page 3

SONET/SDH/ATM OC-48 16:1 TRANSMITTER S3083 OVERVIEW The S3083 transmitter implements SONET/SDH se- rialization and transmission functions. The block dia- gram in Figure 4 shows basic operation of the chip. This chip can be used to implement the front end of ...

Page 4

S3083 S3083 ARCHITECTURE/FUNCTIONAL DESIGN MUX OPERATION The S3083 performs the serializing stage in the pro- cessing of a transmit SONET STS-48 bit serial data stream. It converts the byte serial 155.52 Mbyte/sec data stream to bit serial format at 2.488 ...

Page 5

SONET/SDH/ATM OC-48 16:1 TRANSMITTER FIFO A FIFO is added to decouple the internal and exter- nal (PICLK) clocks. The internally generated divide by 16 clock is used to clock out data from the FIFO. PHINIT and LOCKDET are used to ...

Page 6

S3083 Table 3. Input Pin Assignment and Descriptions ...

Page 7

SONET/SDH/ATM OC-48 16:1 TRANSMITTER Table 3. Input Pin Assignment and Descriptions (Continued ...

Page 8

S3083 Table 4. Output Pin Assignment and Descriptions ...

Page 9

SONET/SDH/ATM OC-48 16:1 TRANSMITTER Table 5. Common Pin Assignment and Description ...

Page 10

S3083 Figure 5. S3083 Pinout 80 PQFP/TEP LSCLKP LSCLKN LVPECLVCC LVPECLGND LLEB LSDP LSDN DLEB RSTB LVPECLGND LLCLKP LLCLKN TESTEN LLDP LLDN LVPECLVCC LVPECLVCC LVPECLGND TTLGND 155MCK 10 SONET/SDH/ATM OC-48 16:1 TRANSMITTER S3083 ...

Page 11

SONET/SDH/ATM OC-48 16:1 TRANSMITTER Figure 6. 80 PQFP/TEP Package TOP VIEW Note: The S3083 package is equipped with an embedded conductive heatsink on the bottom (board side). Active circuitry and vias should not appear in the area immediately under the ...

Page 12

S3083 Table 7. Performance Specifications ...

Page 13

SONET/SDH/ATM OC-48 16:1 TRANSMITTER Table 9. Absolute Maximum Ratings ...

Page 14

S3083 Table 12. LVTTL Input/Output DC Characteristics ...

Page 15

SONET/SDH/ATM OC-48 16:1 TRANSMITTER Table 14. Low Swing Differential CML Output DC Characteristics ...

Page 16

S3083 Table 18. Differential LVPECL Output DC Characteristics ...

Page 17

SONET/SDH/ATM OC-48 16:1 TRANSMITTER Figure 7. Line Loopback Input Timing Diagram LLCLKP LLDP/N Notes on High-Speed LVPECL Input Timing: 1. Timing is measured from the cross-over point of the reference signal to the cross-over point of the input. Table 21. ...

Page 18

S3083 Figure 8. Phase Adjust Timing PHERR PHINIT PCLK PICLK TRANSFER CLK (Internal) 18 SONET/SDH/ATM OC-48 16:1 TRANSMITTER 4-10 BYTE CLOCKS 2 BYTE CLOCKS August 27, 1999 / Revision B ...

Page 19

SONET/SDH/ATM OC-48 16:1 TRANSMITTER Figure 9. External Loop Filter Figure 10. CML Output to +5V PECL Input AC Coupled Termination +3.3V S3083 TSDP/N TSCLKP/N Figure 11. -5V Single Ended ECL Driver to S3083 Input AC Coupled Termination -5.2V ECL August ...

Page 20

S3083 Figure 12. +5V Differential PECL Driver to S3083 Input AC Coupled Termination +5V 330 Figure 13. S3083 to S3083 Terminations +3.3V S3083 PCLKP/N Figure 14. S3083 to S3040/50 Terminations +3.3V S3083 155MCK 20 SONET/SDH/ATM OC-48 16:1 TRANSMITTER 3.3V 0.01 ...

Page 21

SONET/SDH/ATM OC-48 16:1 TRANSMITTER Figure 15. Single-Ended LVPECL Driver to S3083 Input AC Coupled Termination Single-Ended Driver Figure 16. S3083 to S3044 for Diagnostic Loopback +3.3V S3083 LSDP/N LSCLKP/N Figure 17. S3083 to Differential LVPECL 3.3V S3083 PCLKP/N August 27, ...

Page 22

S3083 Figure 18. AC Input Timing PICLKP PIN[15:0] 1. When a set-up time is specified on LVPECL signals between an input and a clock, the set-up time is the time in picoseconds from the 50% point of the input to ...

Page 23

SONET/SDH/ATM OC-48 16:1 TRANSMITTER Ordering Information – 6290 Sequence Drive, San Diego, CA 92121 Phone: (858) 450-9333 • ...

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