S3064 AMCC (Applied Micro Circuits Corp), S3064 Datasheet - Page 5

• Manufacturer Part Number: S3064
• Description: Bicmos Lvpecl Clock Generator Sonet/sdh/atm Oc-12 Transmitter And Receiver Sonet/sdh/atm Oc-48 Differential 1:16 Receiver
• Manufacturer: AMCC (Applied Micro Circuits Corp)

FIFO
A FIFO is added to decouple the internal and exter-
nal (PICLK) clocks. The internally generated divide
by 16 clock is used to clock out data from the FIFO.
PHINIT and LOCKDET are used to center or reset
the FIFO. The PHINIT and LOCKDET signals will
center the FIFO after the third PICLK pulse. This is
in order to insure that PICLK is stable. This scheme
allows the user to have an infinite PCLK to PICLK
delay through the ASIC. Once the FIFO is initilized,
the PCLK to PICLK delay can have a maximum drift
as specified in Table 21.
FIFO Initialization
The FIFO can be initialized in one of the following
three ways:
1. During power up, once the PLL has locked to the
2. When RSTB goes active, the entire chip is reset.
3. The user can also initialize the FIFO by giving a
During the normal running operation, the incoming
data is passed from the PICLK timing domain to the
internally generated divide by 16 clock timing do-
main. Although the frequency of PICLK and the in-
ternally generated clock is the same, their phase
relationship is arbitrary. To prevent errors caused by
short setup or hold times between the two timing
domains, the timing generator circuitry monitors the
phase relationship between PICLK and the internally
August 27, 1999 / Revision B
SONET/SDH/ATM OC-48 16:1 TRANSMITTER
reference clock provided on the REFCLK pins,
the LOCKDET will go active and initialize the
FIFO.
This causes the PLL to go out of lock and thus
the LOCKDET goes inactive. When the PLL reac-
quires the lock, the LOCKDET goes active and
initializes the FIFO. Note: PCLK is held reset
when RSTB is active.
positive edge on PHINIT.
generated clock. When a potential setup or hold time
violation is detected, the phase error goes High.
When PHERR conditions occur, PHINIT should be
activated to recenter the FIFO (at least 2 PCLK peri-
ods). This can be done by connecting PHERR to
PHINIT. When realignment occurs one to three bytes
of data will be lost. The user can also take in the
PHERR signal, process it and send an output to
PHINIT in such a way that idle bytes are lost during
the realignment process. PHERR will go inactive
when the realignment is complete. (See Figure 8.)
OTHER OPERATING MODES
Diagnostic Loopback
When the Diagnostic Loopback Enable (DLEB) input
is active, a loopback from the transmitter to the re-
ceiver at the serial data rate can be set up for diag-
nostic purposes. The differential serial output clock
and data from the transmitter (LSCLK and LSD) is
routed to the input of companion device in place of
the normal data stream (RSCLK and RSD).
Line Loopback
The Line Loopback circuitry consists of alternate
clock and data output drivers. For the S3083, it se-
lects the source of the data and clock which is output
on TSD and TSCLK. When the Line Loopback En-
able input (LLEB) is inactive, it selects data and
clock from the Parallel to Serial Converter block.
When LLEB is active, it forces the output data mul-
tiplexer to select data and clock from the LLD and
LLCLK inputs, and a receive-to-transmit loopback
can be established at the serial data rate.
TSCLK Powerdown
The user is advised not to connect pins 56, 57, 58
and 59 if TSCLKP/N output is not used. This should
be done to reduce the power and to get the best
results on the TSD output.
S3083
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