S8501 AMCC (Applied Micro Circuits Corp), S8501 Datasheet - Page 5

• Manufacturer Part Number: S8501
• Description: Hd-sdi Data Retimer
• Manufacturer: AMCC (Applied Micro Circuits Corp)

Table 3. Response of PLL Loop Circuit to Input Data Rate Variation
Figure 6. Interface Diagram
Table 2. Receiver Operating Modes
December 10, 1999 / Revision C
OE0, OE1
HIGH DEFINITION SERIAL DIGITAL INTERFACE (HD-SDI) CHIPSET
Data Out
D
Data In
(
(
(
a
(
(
M
M
M
M
M
1
a t
CLK
P
4
b
b
b
b
b
L
8
R
p
p
p
p
p
L
5
) s
) s
) s
) s
) s
a
n I
L
L
e t
P
R
o
o
p
e r
E
c
c
t u
Deserializer
k
F
k
Serializer
s
HD-SDI
HD-SDI
e
C
e
e
D
d
d
t n
L
W
W
W
W
W
W
(
(
(
(
(
a
B
B
B
B
B
K
o t
o t
2
a t
d i
d i
d i
d i
d i
o
t i
t i
t i
t i
t i
S
0
d r
) s
) s
) s
h t
h t
h t
h t
h t
) s
) s
a t
e t
F
F
F
F
F
R
e r
e r
e r
e r
e r
e
C
C
C
(
(
(
C
C
(
(
7
e f
M
M
M
q
q
q
q
q
M
M
4
o l
o l
o l
o l
o l
u
u
u
u
u
V
e r
H
H
H
H
H
2 .
c
c
c
e
e
e
c
c
e
e
a
) z
) z
) z
) z
) z
n
5
k
k
k
n
n
n
k
k
n
n
i r
Deserializer
c
c
c
c
c
c
n I
t a
e
HD-SDI
Serializer
y
y
y
y
y
4
2
HD-SDI
p
o i
0
4
0
4
>
>
t u
R
4
8
-
-
R
n
3
7
E
-
-
2
4
C
F
F
F
6
5
F
F
D
c (
F
4
3
4
7
e r
e r
e r
6
2
e r
e r
L
a
C
4
6
8
5
(
(
(
(
(
o
K
7
q
q
q
M
M
M
M
M
q
q
a t
p
p
6
2
L
4
m
R /
p
p
u
u
u
u
u
p
p
H
H
H
H
H
2 .
K
p
p
p
p
e
e
e
e
e
m
m
p
Data Out
CLK
Data In
OE0, OE1
R
C
) z
) z
) z
) z
) z
5
)
n
n
n
n
n
m
p
m
p
a
L
a
c
c
c
c
c
m
m
e r
K
e t
y
y
y
y
y
N
d
o t
When lock is lost, the PLL will attempt to reacquire bit
synchronization, and will shift from the serial input
data to the reference clock so that the correct down-
stream clocking will be maintained. The PLL will
continuously shift between the reference clock and
the input data until input data has been restored. This
will be reflected in the RCLK and the LOCKDETN
outputs – RCLK will shift slightly in frequency, and
LOCKDETN will toggle to show that the PLL is shift-
ing between input data and REFCLK.
In any transfer of PLL control from the serial data to
the reference clock, the RCLK/RCLKN output remains
phase continuous and glitch free, assuring the integ-
rity of downstream clocking.
OTHER OPERATING MODES
Loopback
Local loopback requires a S8401 and a S8501 as
shown in Figure 6. When enabled, serial data from
the S8401 transmitter is sent to the S8501 receiver,
where the clock is extracted and the data is
deserialized. The parallel data is then sent to the
subsystem for verification. This loopback mode pro-
vides the capability to perform offline testing of the
interface to guarantee the integrity of the serial chan-
nel before enabling the transmission medium. It also
allows system diagnostics.
Operating Frequency Range
The S8401 and S8501 are optimized for operation at
the HD-SDI rate of 1.485 Gb/s. A REFCLK must be
selected to be within 100 ppm of the desired byte or
word clock rate.
n I
n I
L
d
d
O
t e
t e
C
H
L
r e
r e
K
—
H
—
L
D
m
m
>
>
H
E
L
n i
n i
T
a
a
N
e t
e t
L
L
L
L
o
o
o
o
k c
k c
k c
k c
n I
n I
e
N
e
d
d
e
e
d
d
e
t e
d
t e
d
S8401/S8501
w
o t
o t
P
r e
r e
o t
o t
L
S
n I
m
m
n i
L
R
R
a t
p
p
n i
n i
E
E
t u
t u
e t
a
a
F
F
e t
e t
C
C
D
d
L
L
a
a
K
K
a t
a t
5