IDT7005L Integrated Device Technology, Inc., IDT7005L Datasheet - Page 10

• Manufacturer Part Number: IDT7005L
• Description: High-speed 8k X 8 Dual-port Static RAM
• Manufacturer: Integrated Device Technology, Inc.

IDT7005S/L
HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM
TIMING WAVEFORM OF WRITE CYCLE NO. 1, R/
TIMING WAVEFORM OF WRITE CYCLE NO. 2,
NOTES:
1. R/
2. A write occurs during the overlap (t
3. t
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the
6. Timing depends on which enable signal is asserted last,
7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured +/- 500mv from steady state with the Output
8. If
9. To access RAM,
CE
ADDRESS
CE
ADDRESS
DATA
Test Load (Figure 2).
to be placed on the bus for the required t
be as short as the specified t
DATA
WR
DATA
OE
or
W
or
is measured from the earlier of
or
SEM
R/
SEM
CE
is Low during R/
OUT
R/
OE
CE
IN
W
IN
W
or
must be high during all address transitions.
(9)
(9)
SEM
Low transition occurs simultaneously with or after the R/
CE
= V
W
controlled write cycle, the write pulse width must be the larger of t
IH and
t
WP
AS
t
AS
SEM
(6)
.
(6)
EW
CE
= V
(4)
or t
or R/
IL.
DW
WP
To access semaphore
. If
W
) of a Low
(or
OE
SEM
is High during an R/
t
WZ
CE
t
or R/
(7)
t
AW
AW
CE
t
WC
t
and a Low R/
WC
W
or R/
) going High to the end of write cycle.
t
t
EW
WP
,
W
CE
(2)
(2)
.
W
= V
6.06
CE CE CE CE CE
W
controlled write cycle, this requirement does not apply and the write pulse can
W
IH
W W W W W
for memory array writing cycle.
Low transition, the outputs remain in the High-impedance state.
and
CONTROLLED TIMING
CONTROLLED TIMING
t
t
DW
DW
SEM
= V
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IL.
WP
t
t
WR
EW
or (t
(3)
must be met for either condition.
WZ
t
t
t
DH
DH
+ t
WR
t
DW
OW
(3)
) to allow the I/O drivers to turn off and data
(1,5)
(1,5,8)
t
HZ
(7)
(4)
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2738 drw 09
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