IDT7005L Integrated Device Technology, Inc., IDT7005L Datasheet - Page 16

• Manufacturer Part Number: IDT7005L
• Description: High-speed 8k X 8 Dual-port Static RAM
• Manufacturer: Integrated Device Technology, Inc.

IDT7005S/L
HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM
TRUTH TABLE II —
ADDRESS BUSY ARBITRATION
NOTES:
1. Pins
2. 'L' if the inputs to the opposite port were stable prior to the address and enable inputs of this port. 'H' if the inputs to the opposite port became stable after
3. Writes to the left port are internally ignored when
TRUTH TABLE III — EXAMPLE OF SEMAPHORE PROCUREMENT SEQUENCE
NOTES:
1. This table denotes a sequence of events for only one of the eight semaphores on the IDT7005.
2. There are eight semaphore flags written to via I/O
FUNCTIONAL DESCRIPTION
address and I/O pins that permit independent access for reads
or writes to any location in memory. The IDT7005 has an
automatic power down feature controlled by
controls on-chip power down circuitry that permits the respec-
tive port to go into a standby mode when not selected (
high). When a port is enabled, access to the entire memory
array is permitted.
INTERRUPTS
location (mail box or message center) is assigned to each port.
The left port interrupt flag (
writes to memory location 1FFE (HEX), where a write is
defined as
clears the interrupt through access of address location 1FFE
when
Likewise, the right port interrupt flag (
CE CE CE CE CE
No Action
Left Port Writes "0" to Semaphore
Right Port Writes "0" to Semaphore
Left Port Writes "1" to Semaphore
Left Port Writes "0" to Semaphore
Right Port Writes "1" to Semaphore
Left Port Writes "1" to Semaphore
Right Port Writes "0" to Semaphore
Right Port Writes "1" to Semaphore
Left Port Writes "0" to Semaphore
Left Port Writes "1" to Semaphore
X
H
X
L
IDT7005 are push-pull, not open drain outputs. On slaves the
the address and enable inputs of this port. If t
simultaneously.
internally ignored when
The IDT7005 provides two ports with separate control,
If the user chooses to use the interrupt function, a memory
L
CE
BUSY
CE CE CE CE CE
X
X
H
L
=
Inputs
R
CE
L
OE
and
Functions
NO MATCH
= R/
A
A
= V
MATCH
MATCH
MATCH
0R
0L
BUSY
-A
-A
W
IL.
12L
12R
= V
R
For this example, R/
BUSY
are both outputs when the part is configured as a master. Both are inputs when configured as a slave.
IL
INT
BUSY
BUSY
BUSY
BUSY
BUSY
per the Truth Table . The left port
R
outputs are driving low regardless of actual logic level on the pin.
(2)
L
H
H
H
) is asserted when the right port
L
Outputs
(1)
BUSY
BUSY
BUSY
BUSY
BUSY
INT
D
(2)
H
H
H
0
R
APS
- D
R
W
) is asserted when
(1)
BUSY
0
1
0
0
1
1
0
1
1
1
0
1
7
is not met, either
is a "don't care".
and read from all I/O
Left
Normal
Normal
Normal
Write Inhibit
CE
L
outputs are driving low regardless of actual logic level on the pin. Writes to the right port are
Function
. The
2738 tbl 18
BUSY
D
0
- D
CE
CE
(3)
BUSY
X
7
6.06
input internally inhibits writes.
1
1
1
0
0
1
1
0
1
1
1
's
Right
(I/O
the left port writes to memory location 1FFF (HEX) and to clear
the interrupt flag (
location 1FFF. The message (8 bits) at 1FFE or 1FFF is user-
defined, since it is an addressable SRAM location. If the
interrupt function is not used, address locations 1FFE and
1FFF are not used as mail boxes, but as part of the random
access memory. Refer to Truth Table for the interrupt opera-
tion.
BUSY LOGIC
of the RAM have accessed the same location at the same
time. It also allows one of the two accesses to proceed and
signals the other side that the RAM is “Busy”. The busy pin can
then be used to stall the access until the operation on the other
side is completed. If a write operation has been attempted
from the side that receives a busy indication, the write signal
is gated internally to prevent the write from proceeding.
L
or
0-
Busy Logic provides a hardware indication that both ports
BUSY
I/O
7
Semaphore free
Left port has semaphore token
No change. Right side has no write access to semaphore
Right port obtains semaphore token
No change. Left port has no write access to semaphore
Left port obtains semaphore token
Semaphore free
Right port has semaphore token
Semaphore free
Left port has semaphore token
Semaphore free
). These eight semaphores are addressed by A
R
= Low will result.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
INT
R
), the right port must read the memory
BUSY
Status
L
and
BUSY
(1,2)
R
outputs can not be low
BUSY
0
- A
X
outputs on the
2
.
2738 tbl 19
16