S2050 AMCC (Applied Micro Circuits Corp), S2050 Datasheet - Page 3

• Manufacturer Part Number: S2050
• Description: Bicmos Pecl Clock Gigabit Ethernet Chipset
• Manufacturer: AMCC (Applied Micro Circuits Corp)

The parallel input data word can be either 10 bits or
20 bits wide, depending upon DWS pin selection. A
block diagram showing the basic chip function is
shown in Figure 3.
Parallel/Serial Conversion
The parallel-to-serial converter takes in 10-bit or 20-
bit wide data from the input latch and converts it to a
serial data stream. Parallel data is latched into the
transmitter on the positive going edge of REFCLK.
The data is then clocked synchronous to the clock
synthesis unit serial clock into the serial output shift
register. The shift register is clocked by the internally
generated bit clock which is 10 or 20 times the
REFCLK input frequency. The state of the serial out-
puts is controlled by the output enable pins, OE0 and
OE1. D[10] is transmitted first in 10-bit mode. D[0] is
transmitted first in 20-bit mode. Table 2 shows the
mapping of the parallel data to the 8B/10B codes.
March 29, 2000 / Revision B
Figure 4. S2050 Functional Block Diagram
GIGABIT ETHERNET CHIPSET
LOCKREFN
Table 2. Data Mapping to 8B/10B Alphabetic Representation
T
R
8
e r
SYNCEN
B
X
REFCLK
X
REFSEL
p
1 /
0 [
0 [
e r
0
1 :
LPEN
1 :
s
DWS
B
e
RLX
RLY
] 9
] 9
t n
RX
RY
a
r o
p l
t a
h
o i
a
n
b
e
c i t
0
a
CONTROL
First bit transmitted in 20-bit mode
LOGIC
1
b
2:1
2
c
F
3
d
r i
t s
4
e
D
a
a t
5
f
B
y
6
g
RECOVERY
e t
PLL CLOCK
7
h
8
i
9
10-Bit/20-Bit Mode
The S2046 operates with either 10-bit or 20-bit paral-
lel data inputs. Word width is selectable via the DWS
pin. In 10-bit mode, D[10-19] are used and D[0-9] are
ignored. See Table 2.
Reference Clock Input
The reference clock input (REFCLK) must be supplied
with a PECL single-ended AC coupled crystal clock
source with 100 PPM tolerance to assure that the trans-
mitted data meets the proposed 802.3z Specification
frequency limits. The internal serial clock is frequency
locked to the reference clock. Refer to Table 1 for
reference clock frequencies.
Table 1. Transmitter Operating Modes
j
DWS
0
1
BITCLK
1
a
0
REFSEL
First bit transmitted in 10-bit mode
1
D
b
1
REGISTER
0
1
SHIFT
1
c
2
(Mbps/sec)
DETECT
DIVIDER
Data Rate
LOGIC
SYNC
S
1250.0
1250.0
1
e
d
3
c
o
n
1
e
d
4
D
1
Word
Width
a
D
(Bits)
f
5
a t
20
10
B
1
g
Q
y
6
Frequency
e t
Reference
Clock
(MHz)
1
125.0
20
62.5
h
7
S2046/S2050
1
i
8
LOCKDETN
D(0:19)
SYNC
RCLK
RCLKN
TCLK/TCLKN
Frequency
1
j
9
(MHz)
62.5
62.5
3