ADP3207 ANALOG DEVICES, ADP3207 Datasheet - Page 14

• Manufacturer Part Number: ADP3207
• Description: 7-Bit Programmable Multiphase Mobile CPU Synchronous Buck Controller
• Manufacturer: ANALOG DEVICES

ADP3207
Following the IMVP-6 specification, PWRGD window is
defined as −300 mV below and +200 mV above the actual VID
DAC output voltage. For any DAC voltage below 300 mV, only
the upper limit of the PWRGD window is monitored. To
prevent false alarm, the power-good circuit is masked during
various system transitions, including any VID change and
entrance/exit out of deeper sleep. The duration of the PWRGD
mask is set by an internal timer to be about 100 µs. In
conditions where a larger than 200 mV voltage drop occurs
during deeper sleep entry or slow deeper sleep exit, the duration
of PWRGD masking is extended by an internal logic circuit.
POWER-UP SEQUENCE AND SOFT START
The power-on ramp-up time of the output voltage is set with a
capacitor tied from the SS pin to GND. The capacitance on the
SS pin also determines the current-limit latch-off time as
explained in the Soft Transient section. The whole power-up
sequence, including soft start, is illustrated in Figure 9.
In VCC UVLO or in shutdown, the SS pin is held at zero
potential. When VCC ramps above the upper UVLO threshold
and EN is asserted high, the ADP3207 enables internal bias and
starts a reset cycle that lasts about 50 μs to 60 µs. Next, when
initial reset is over, the chip detects the number of phases set by
the user, and gives a go signal to ramp up the SS voltage. During
soft start, the external SS capacitor is charged by an internal
8 µA current source. The V
voltage up to the V
burnt-in VID code (the 1.2 V code by IMVP-6 specification).
While V
continues to rise. When the SS pin voltage reaches 1.7 V, the
ADP3207 asserts the CLKEN signal low, given that the V
voltage is within the power-good window of V
ADP3207 reads the VID codes provided by the CPU on VID0
to VID6 input pins. The V
the VID voltage by a well controlled soft transition, as
introduced in the Soft Transient section. Meanwhile, the SS pin
voltage is quickly charged up to a clamp voltage of 2.9 V.
The PWRGD signal is not asserted until there is a t
delay of about 3 ms to 10 ms as specified by the IMVP-6. The
power-good delay can be programmed by the capacitor
connected from PGDELAY to GND. Before the CLKEN signal
is asserted low, PGDELAY is reset to zero. After the assertion of
the CLKEN signal, an internal source current of 2 µA starts
charging up the external capacitor on the PGDELAY pin.
Assuming the V
window defined by the VID DAC voltage, the PWRGD signal is
asserted high when the PGDELAY voltage reaches the 2.9 V
power-good delay termination threshold.
If either EN is taken low or VCC drops below the lower VCC
UVLO threshold, then both the SS capacitor and PGDELAY
capacitor are reset to ground to be ready for another soft-start cycle.
CORE
is being regulated at V
CORE
BOOT
voltage is settled within the power-good
voltage level, which is determined by a
CORE
CORE
voltage changes from V
voltage follows the ramping SS
BOOT
voltage, the SS capacitor
BOOT
. The
CPU_PWRGD
BOOT
CORE
to
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SOFT TRANSIENT
The ADP3207 provides a soft transient function to reduce inrush
current during various transitions, including the entrance/exit of
deeper sleep and the transition from V
Reducing the inrush current helps decrease the acoustic noise
generated by the MLCC input capacitors and inductors.
The soft transient feature is implemented with an STSET buffer
amplifier that outputs constant sink or source current on the
STSET pin where an external capacitor is connected. The
capacitor is used to program the slew rate of V
during any VID voltage transient. During steady-state
operation, both the reference input of the voltage error
amplifier and the STSET amplifier are connected to the VID
DAC output. Consequently, the STSET voltage is a buffered
version of VID DAC output. When system signals trigger a soft
transition, the reference input of the voltage error amplifier
switches from the DAC output to the STSET output, while the
input of the STSET amplifier remains connected to the DAC.
The STSET buffer input sees the almost instantaneous VID
voltage change and tries to track it. Tracking is not
instantaneous because the buffer slew rate is limited by the
source/sink current capability of the STSET output. Therefore,
V
a controlled slew rate. When the transient period is complete,
the reference input of the voltage amplifier switches back to the
VID DAC output to ensure higher accuracy.
CORE
PWRGD
CLKEN
V
CORE
VCC
EN
voltage follows the VID DAC output voltage change with
SS
Figure 9. Power-Up Sequence
1.2V
2.9V
1.7V
V
BOOT
BOOT
V
t
CPU_PWRGD
VID
to VID voltage.
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CORE
voltage