ADP3207 ANALOG DEVICES, ADP3207 Datasheet - Page 25

• Manufacturer Part Number: ADP3207
• Description: 7-Bit Programmable Multiphase Mobile CPU Synchronous Buck Controller
• Manufacturer: ANALOG DEVICES

SETTING THE SWITCHING FREQUENCY FOR RPM
MODE OPERATION OF PHASE 1
During the RPM mode operation of Phase 1, the ADP3207 runs
in pseudo constant frequency, given that the load current is
high enough for continuous current mode. While in
discontinuous current mode, the switching frequency is
reduced with the load current in a linear manner. When
considering power conversion efficiency in light load, lower
switching frequency is usually preferred for RPM mode.
However, the V
limitation for lowest switching frequency. Therefore, depending
on the inductor and output capacitors, the switching frequency
in RPM mode can be equal, larger, or smaller than its
counterpart in PWM mode.
A resistor between VRPM and RRPM pins sets the pseudo
constant frequency as following:
where:
A
C
R
internal ramp magnitude.
Because R
switching frequency in RPM operation.
CURRENT-LIMIT SETPOINT
To select the current-limit setpoint, we need to find the resistor
value for R
set with a 1.7 V source (V
13 mV/µA. R
For values of R
lower than expected, so some adjustment of R
needed. Here, I
the supply. In this example, if choosing 55 A for I
190 kΩ, which is close to a standard 1% resistance of 191 kΩ.
The per-phase current limit described earlier has its limit
determined by the following:
R
R
R
is an external resistor on the RAMPADJ pin to set the
is the internal ramp amplifier gain.
is the internal ramp capacitor value.
R
R
R
I
PHLIM
RPM
RPM
LIM
=
R
=
=
LIM
≅
= 280 kΩ, the following resistance sets up 300 kHz
A
V
. 1
I
V
LIM
LIM
VID
. The current-limit threshold for the ADP3207 is
LIM
150
2
COMP
2
LIM
LIM
CORE
×
×
×
can be found using the following equation:
×
+
237
V
A
R
V
greater than 500 kΩ, the current limit may be
1
R
is the average current limit for the output of
(
D
MAX
T
LIM
0 .
+
ripple specification in the IMVP-6 sets the
O
×
1
k
V
R
Ω
0 .
)
−
DS
×
V
V
(
A
LIM
MAX
×
R
R
R
−
280
) across R
0
×
)
R
V
2 .
1 (
×
BIAS
k
×
C
−
Ω
1 (
R
D
+
×
−
×
)
I
7
2
×
. 0
R
f
SW
pF
V
LIM
061
VID
×
)
with a gain of
300
×
−
. 1
0
150
kHz
LIM
5 .
k
may be
LIM
Ω
−
, R
500
LIM
Ω
is
=
80
(24)
(25)
(26)
Rev. 0 | Page 25 of 32
6 .
k
Ω
For the ADP3207, the maximum COMP voltage (V
3.3 V, the COMP pin bias voltage (V
current balancing amplifier gain (A
and a R
results in a per-phase limit of 85 A. Although this number
seems high, this current level can only be reached with a
absolute short at the output and the current-limit latch-off
function shutting down the regulator before overheating occurs.
This limit can be adjusted by changing the ramp voltage V
However, users should not set the per-phase limit lower than
the average per-phase current (I
There is also a per-phase initial duty-cycle limit at maximum
input voltage:
For this example, the duty-cycle limit at maximum input voltage
is found to be 0.25 when D is 0.061.
FEEDBACK LOOP COMPENSATION DESIGN
Optimized compensation of the ADP3207 allows the best
possible response of the regulator’s output to a load change. The
basis for determining the optimum compensation is to make
the regulator and output decoupling appear as an output
impedance that is entirely resistive over the widest possible
frequency range, including dc, and equal to the droop resistance
(R
droops in proportion with the load current at any load current
slew rate. This ensures the optimal positioning and minimizes
the output decoupling.
With the multimode feedback structure of the ADP3207, users
need to set the feedback compensation to make the converter
output impedance work in parallel with the output decoupling.
Several poles and zeros are created by the output inductor and
decoupling capacitors (output filter) that need to be
compensated for.
A type-three compensator on the voltage feedback is adequate
for proper compensation of the output filter. Equation 28 to
Equation 36 is intended to yield an optimal starting point for
the design; some adjustments can be necessary to account for
PCB and component parasitic effects (see the Tuning Procedure
for ADP3207).
O
). With the resistive output impedance, the output voltage
D
LIM
DS(MAX)
=
D
MIN
of 3.8 mΩ (low-side on-resistance at 150°C)
×
V
COMP
(
MAX
V
R
)
−
V
LIM
BIAS
/n).
D
BIAS
) is 5. Using a V
) is 1.0 V, and the
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ADP3207
COMP(MAX)
R
of 0.55 V,
R
.
) is
(27)