ADP3207 ANALOG DEVICES, ADP3207 Datasheet - Page 20

• Manufacturer Part Number: ADP3207
• Description: 7-Bit Programmable Multiphase Mobile CPU Synchronous Buck Controller
• Manufacturer: ANALOG DEVICES

ADP3207
APPLICATION INFORMATION
The design parameters for a typical Intel IMVP6-compliant
CPU Core VR application are as follows:
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•
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SETTING THE CLOCK FREQUENCY FOR PWM
MODE
In PWM mode operation, The ADP3207 uses a fixed-frequency
control architecture. The frequency is set by an external timing
resistor (R
determine the switching frequency per phase, which directly
relates to switching losses, and the sizes of the inductors and
input and output capacitors. In a 2-phase design, a clock
frequency of 560 kHz sets the switching frequency to 280 kHz
per phase. This selection represents a trade-off between the
switching losses and the minimum sizes of the output filter
components. To achieve a 560 kHz oscillator frequency at VID
voltage 1.150 V, R
R
where 16 pF and 25 kΩ are internal IC component values. For
good initial accuracy and frequency stability, it is recommended
to use a 1% resistor.
SOFT-START AND CURRENT-LIMIT LATCH-OFF
DELAY TIMES
The soft-start and current-limit latch-off delay functions share
the SS pin. Consequently, these two parameters must be
considered together. The first step is to set C
ramp. This ramp is generated with a 8 µA internal current
source. The value for C
T
can be calculated using
Maximum input voltage (V
Minimum input voltage (V
Output voltage by VID setting (V
Maximum output current (I
Load line slope (R
Maximum output current step (ΔI
Maximum output thermal current (I
Number of phases (n) = 2
Switching frequency per phase (f
Duty cycle at maximum input voltage (D
Duty cycle at minimum input voltage (D
R
T
=
T
n
). The clock frequency and the number of phases
V
×
VID
f
SW
+
T
1
×
0 .
16
has to be 237 kΩ. Alternatively, the value for
V
pF
O
SS
) = 2.1 mΩ
−
can be set as
5
k
Ω
INMIN
INMAX
O
) = 44 A
) = 7 V
) = 19 V
SW
VID
O
) = 280 kHz
) = 34.5 A
) = 1.150 V
OTDC
SS
) = 32 A
MAX
MIN
for the soft-start
) = 0.061
) = 0.164
Rev. 0 | Page 20 of 32
(1)
where:
V
specification as 1.2 V.
t
in the IMVP-6 specification.
Assuming a desired soft-start time of 2 ms, C
the closest standard capacitance at 12 nF.
Once C
equal to 7.2 ms according to the following calculation:
PWRGD DELAY TIMER
The PWRGD delay, t
specification as the time period between the CLKEN assertion
and the PWRGD assertion. It is programmed by a cap on the
PGDELAY pin.
The IMVP-6 specifies that the PWRGD delay is between 3 ms
to 20 ms. Assuming 7 ms PWRGD delay is preferred, then
C
INDUCTOR SELECTION
The choice of inductance determines the ripple current in the
inductor. Less inductance leads to more ripple current, which
increases the output ripple voltage and conduction losses in the
MOSFETs. However, this allows the use of smaller-size inductors,
and for a specified peak-to-peak transient deviation, it allows
less total output capacitance. Conversely, a higher inductance
means lower ripple current and reduced conduction losses, but
requires larger size inductors and more output capacitance for
the same peak-to-peak transient deviation. In a multiphase
converter, the practical peak-to-peak inductor ripple current is
less than 50% of the maximum dc current in the same inductor.
Equation 5 shows the relationship between the inductance,
oscillator frequency, and peak-to-peak ripple current. Equation
6 can be used to determine the minimum inductance based on
a given output ripple voltage.
SS
BOOT
PGDLY
is the desired soft-start time, recommended to be below 3 ms
C
t
C
I
L
is the boot voltage for the CPU, defined in the IMVP-6
DELAY
R
SS
PGDLY
is 4.7 nF.
≥
SS
=
=
V
has been chosen, the current-limit latch-off time is
V
VID
8
VID
=
V
=
μA
1
×
BOOT
1
×
2 .
f
SW
R
×
9 .
(
1
V
2
O
t
μA
SS
−
×
μA
×
×
D
L
(
C
×
1
2
f
CPU_PWRGD
SS
t
MIN
−
9 .
SW
CPU
(
V
n
)
×
_ PWRGD
×
V
D
RIPPLE
MIN
, is defined in the IMVP-6
))
×
(
1
−
D
MIN
)
SS
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is 13.3 nF, with
(2)
(3)
(4)
(5)
(6)