ADZS-BF537-EZLITE Analog Devices, ADZS-BF537-EZLITE Datasheet

ADZS-BF537-EZLITE

Manufacturer Part Number

ADZS-BF537-EZLITE

Description

Specifications: Type: DSP ; Contents: Evaluation Board, Software and Documentation ; For Use With/Related Products: ADSP-BF537 ; Lead Free Status: Lead Free ; RoHS Status: RoHS Compliant

Manufacturer

Analog Devices

Datasheet

1.ADZS-BF537-EZLITE.pdf (68 pages)

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FEATURES

Up to 600 MHz high performance Blackfin processor

Wide range of operating voltages (see

Qualified for Automotive Applications (see

Programmable on-chip voltage regulator

182-ball and 208-ball CSP_BGA packages

MEMORY

Up to 132K bytes of on-chip memory

External memory controller with glueless support for SDRAM

Flexible booting options from external flash, SPI and TWI

Memory management unit providing memory protection

Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc.

Rev. I

Information furnished by Analog Devices is believed to be accurate and reliable.

However, no responsibility is assumed by Analog Devices for its use, nor for any

infringements of patents or other rights of third parties that may result from its use.

Specifications subject to change without notice. No license is granted by implication

or otherwise under any patent or patent rights of Analog Devices. Trademarks and

registered trademarks are the property of their respective owners.

Three 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs,

RISC-like register and instruction model for ease of

Advanced debug, trace, and performance monitoring

on Page

ucts on Page

Instruction SRAM/cache and instruction SRAM

Data SRAM/cache plus additional dedicated data SRAM

Scratchpad SRAM (see

and asynchronous 8-bit and 16-bit memories

memory or from SPI, TWI, and UART host devices

40-bit shifter

programming and compiler-friendly support

memory configurations)

24)

67)

VOLTAGE REGULATOR

INSTRUCTION

MEMORY

Table 1 on Page 3

EXTERNAL ACCESS BUS

FLASH, SDRAM CONTROL

EXTERNAL PORT

Operating Conditions

MEMORY

DATA

Automotive Prod-

for available

JTAG TEST AND EMULATION

DMA CORE BUS

Figure 1. Functional Block Diagram

ADSP-BF534/ADSP-BF536/ADSP-BF537

CONTROLLER

BOOT ROM

INTERRUPT

DMA

PERIPHERAL ACCESS BUS

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

PERIPHERALS

IEEE 802.3-compliant 10/100 Ethernet MAC (ADSP-BF536 and

Controller area network (CAN) 2.0B interface

Parallel peripheral interface (PPI), supporting ITU-R 656

2 dual-channel, full-duplex synchronous serial ports

12 peripheral DMAs, 2 mastered by the Ethernet MAC

2 memory-to-memory DMAs with external request lines

Event handler with 32 interrupt inputs

Serial peripheral interface (SPI) compatible

2 UARTs with IrDA support

2-wire interface (TWI) controller

Eight 32-bit timer/counters with PWM support

Real-time clock (RTC) and watchdog timer

32-bit core timer

48 general-purpose I/Os (GPIOs), 8 with high current drivers

On-chip PLL capable of frequency multiplication

Debug/JTAG interface

ADSP-BF537 only)

video data formats

(SPORTs), supporting 8 stereo I

WATCHDOG TIMER

ETHERNET MAC

(See Table 1)

TIMER7-0

UART0-1

SPORT0

SPORT1

CAN

RTC

TWI

PPI

SPI

Embedded Processor

PORT G

PORT J

PORT F

PORT H

GPIO

S channels

www.analog.com

Blackfin

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