ADZS-BF537-EZLITE Analog Devices, ADZS-BF537-EZLITE Datasheet - Page 46

• Manufacturer Part Number: ADZS-BF537-EZLITE
• Description: Specifications: Type: DSP ; Contents: Evaluation Board, Software and Documentation ; For Use With/Related Products: ADSP-BF537 ; Lead Free Status: Lead Free ; RoHS Status: RoHS Compliant
• Manufacturer: Analog Devices

ADSP-BF534/ADSP-BF536/ADSP-BF537
Timer Clock Timing
Table 37
Table 37. Timer Clock Timing
Timer Cycle Timing
Table 38
input signal is asynchronous in “width capture mode” and
“external clock mode” and has an absolute maximum input fre-
quency of (f
Table 38. Timer Cycle Timing
1
2
3
4
5
Parameter
Switching Characteristic
t
Parameter
Timing Characteristics
t
t
t
t
Switching Characteristics
t
t
Applies to all nonautomotive-grade devices when operated within either of these voltage ranges.
Applies to all nonautomotive-grade devices when operated within these voltage ranges.
All automotive-grade devices are within these specifications.
The minimum pulse widths apply for TMRx signals in width capture and external clock modes. They also apply to the PF15 or PPI_CLK signals in PWM output mode.
Either a valid setup and hold time or a valid pulse width is sufficient. There is no need to resynchronize programmable flag inputs.
TODP
WL
WH
TIS
TIH
HTO
TOD
and
and
Timer Pulse Width Input Low (Measured In SCLK Cycles)
Timer Pulse Width Input High (Measured In SCLK Cycles)
Timer Input Setup Time Before CLKOUT Low
Timer Input Hold Time After CLKOUT Low
Timer Pulse Width Output (Measured In SCLK Cycles)
Timer Output Update Delay After CLKOUT High
SCLK
Figure 27
Figure 28
/2) MHz.
TMRx OUTPUT
TMRx OUTPUT
Timer Output Update Delay After PPI_CLK High
TMRx INPUT
PPI_CLK
CLKOUT
describe timer clock timing.
describe timer expired operations. The
5
Rev. I | Page 46 of 68 | July 2010
5
t
TIS
Figure 27. Timer Clock Timing
Figure 28. Timer Cycle Timing
t
WH
,t
4
WL
t
4
TIH
Min
1 × t
1 × t
5.5
1.5
1 × t
0.80 V V
2.25 V V
SCLK
SCLK
SCLK
t
TOD
DDINT
DDEXT
or
Max
(2
6.5
32
–1) × t
0.95 V
2.70 V
t
HTO
t
TODP
SCLK
1
Min
1 × t
1 × t
1 × t
5.0
1.5
0.95 V V
Min
2.70 V V
SCLK
SCLK
SCLK
DDINT
and
DDEXT
Max
(2
6.0
Max
12
32
–1) × t
1.43 V
3.60 V
SCLK
2, 3
Unit
Unit
ns
ns
ns
ns
ns
ns
ns