ADZS-BF537-EZLITE Analog Devices, ADZS-BF537-EZLITE Datasheet - Page 53

• Manufacturer Part Number: ADZS-BF537-EZLITE
• Description: Specifications: Type: DSP ; Contents: Evaluation Board, Software and Documentation ; For Use With/Related Products: ADSP-BF537 ; Lead Free Status: Lead Free ; RoHS Status: RoHS Compliant
• Manufacturer: Analog Devices

TEST CONDITIONS
All timing parameters appearing in this data sheet were
measured under the conditions described in this section.
Figure 48
(other than output enable/disable). The measurement point is
V
Output Enable Time
Output pins are considered to be enabled when they have made
a transition from a high impedance state to the point when they
start driving. The output enable time t
the point when a reference signal reaches a high or low voltage
level to the point when the output starts driving as shown in the
Output Enable/Disable diagram
t
switches to when the output voltage reaches 2.0 V (output high)
or 1.0 V (output low). Time t
output starts driving to when the output reaches the 1.0 V or
2.0 V trip voltage. Time t
the equation:
If multiple pins (such as the data bus) are enabled, the measure-
ment value is that of the first pin to start driving.
ENA_MEASURED
OUTPUT
MEAS
INPUT
OR
Figure 48. Voltage Reference Levels for AC Measurements (Except
Output Enable/Disable)
= V
V
shows the measurement point for ac measurements
DDEXT
MEAS
is the interval from when the reference signal
/2.
t
ENA
=
ENA
t
ENA_MEASURED
is calculated as shown in
TRIP
(Figure
is the interval from when the
ENA
–
49). The time
t
is the interval from
TRIP
V
MEAS
Rev. I | Page 53 of 68 | July 2010
Output Disable Time
Output pins are considered to be disabled when they stop driv-
ing, go into a high impedance state, and start to decay from their
output high or low voltage. The time for the voltage on the bus
to decay by V is dependent on the capacitive load, C
load current, I
the equation:
The output disable time t
t
t
switches to when the output voltage decays V from the mea-
sured output-high or output-low voltage. The time t
calculated with the test loads C
equal to 0.5 V.
Example System Hold Time Calculation
To determine the data output hold time in a particular system,
first calculate t
to be the difference between the processor’s output voltage and
the input threshold for the device requiring the hold time. A
typical V is 0.4 V. C
and I
The hold time is t
example, t
ADSP-BF534/ADSP-BF536/ADSP-BF537
DIS_MEASURED
DIS_MEASURED
(MEASURED)
(MEASURED)
t
DIS
V
V
L
OH
OL
is the total leakage or three-state current (per data line).
OUTPUT STOPS DRIVING
DSDAT
and t
is the interval from when the reference signal
L
DECAY
. This decay time can be approximated by
for an SDRAM write cycle).
Figure 49. Output Enable/Disable
DECAY
DECAY
REFERENCE
t
V
V
DIS_MEASURED
OH
OL
SIGNAL
using the equation given above. Choose V
t
L
t
DECAY
(MEASURED)
DECAY
is the total bus capacitance (per data line),
(MEASURED) + V
plus the minimum disable time (for
as shown in
DIS
HIGH IMPEDANCE STATE
is the difference between
=
L
and I
t
C
ENA
L
Figure
V
V
L
, and with V
OUTPUT STARTS DRIVING
I
L
49. The time
t
ENA_MEASURED
V
V
TRIP
TRIP
t
TRIP
(LOW)
V
V
(HIGH)
OH
OL
DECAY
L
(MEASURED)
(MEASURED)
, and the
is