ADZS-BF537-EZLITE Analog Devices, ADZS-BF537-EZLITE Datasheet - Page 49

• Manufacturer Part Number: ADZS-BF537-EZLITE
• Description: Specifications: Type: DSP ; Contents: Evaluation Board, Software and Documentation ; For Use With/Related Products: ADSP-BF537 ; Lead Free Status: Lead Free ; RoHS Status: RoHS Compliant
• Manufacturer: Analog Devices

Table 44. 10/100 Ethernet MAC Controller Timing: MII/RMII Asynchronous Signal
1
2
Table 45. 10/100 Ethernet MAC Controller Timing: MII Station Management
1
Parameter
t
t
t
t
MII/RMII asynchronous signals are COL, CRS. These signals are applicable in both MII and RMII modes. The asynchronous COL input is synchronized separately to both
The asynchronous CRS input is synchronized to the ETxCLK, and must have a minimum pulse width high or low at least 1.5 times the period of ETxCLK.
Parameter
t
t
t
t
MDC/MDIO is a 2-wire serial bidirectional port for controlling one or more external PHYs. MDC is an output clock whose minimum period is programmable as a multiple
ECOLH
ECOLL
ECRSH
ECRSL
the ETxCLK and the ERxCLK, and must have a minimum pulse width high or low at least 1.5 times the period of the slower of the two clocks.
MDIOS
MDCIH
MDCOV
MDCOH
of the system clock SCLK. MDIO is a bidirectional data line.
1, 2
1
COL Pulse Width High
COL Pulse Width Low
CRS Pulse Width High
CRS Pulse Width Low
MDIO Input Valid to MDC Rising Edge (Setup)
MDC Rising Edge to MDIO Input Invalid (Hold)
MDC Falling Edge to MDIO Output Valid
MDC Falling Edge to MDIO Output Invalid (Hold)
ERx_CLK
ERxD3–0
ERxDV
ERxER
MIITxCLK
ETxD3–0
ETxEN
Figure 31. 10/100 Ethernet MAC Controller Timing: MII Transmit Signal
Figure 30. 10/100 Ethernet MAC Controller Timing: MII Receive Signal
t
ERXCLKIS
t
ERXCLKIH
Rev. I | Page 49 of 68 | July 2010
t
t
ETXCLKOH
ERXCLKW
t
ETXCLKW
t
ETXCLKOV
t
ERXCLK
t
ETXCLK
ADSP-BF534/ADSP-BF536/ADSP-BF537
Min
t
t
t
t
t
t
Min
10
10
25
–1
ETxCLK
ERxCLK
ETxCLK
ERxCLK
ETxCLK
ETxCLK
× 1.5
× 1.5
× 1.5
× 1.5
× 1.5
× 1.5
Max
Max
Unit
ns
ns
ns
ns
ns
ns
Unit
ns
ns
ns
ns