CDK2000 Cirrus Logic, Inc., CDK2000 Datasheet - Page 12

• Manufacturer Part Number: CDK2000
• Description: Fractional-n Clock Multiplier with Internal LCO
• Manufacturer: Cirrus Logic, Inc.

12
SDATA
SDATA
to as wander. In others it may be preferable to remove only higher frequency jitter, allowing the input wan-
der to pass through the PLL without attenuation.
Typically, applications in which the PLL_OUT signal creates a new clock domain from which all other sys-
tem clocks and associated data are derived will benefit from the maximum jitter and wander rejection of
the lowest PLL bandwidth setting. See
Systems in which some clocks and data are derived from the PLL_OUT signal while other clocks and data
are derived from the CLK_IN signal will often require phase alignment of all the clocks and data in the
system. See
necessary to increase the minimum loop bandwidth allowing this wander to pass through to the CLK_OUT
signal in order to maintain phase alignment. For these applications, it is advised to experiment with the
loop bandwidth settings and choose the lowest bandwidth setting that does not produce system timing
errors due to wandering between the clocks and data synchronous to the CLK_IN domain and those syn-
chronous to the PLL_OUT domain.
While acquiring lock, the digital loop bandwidth is automatically set to a large value. Once lock is
achieved, the digital loop bandwidth will settle to the minimum value selected by the ClkIn_BW[2:0] pa-
rameter.
MCLK
LRCK
SCLK
Referenced Control
ClkIn_BW[2:0]
MCLK
LRCK
SCLK
Wander < 128 Hz
Wander > 1 Hz
.......................“Clock Input Bandwidth (ClkIn_BW[2:0])” on page 21
Figure
D0
D0
Figure 9. High bandwidth with CLK_IN domain re-use
9. If there is substantial wander on the CLK_IN signal in these applications, it may be
Figure 8. Low bandwidth and new clock domain
Jitter
Jitter
Parameter Definition
D1
D1
CLK_IN
CLK_IN
or
or
BW = 128 Hz
Figure
BW = 1 Hz
PLL
Subclocks and data re-used
from previous clock domain.
PLL
8.
from new clock domain.
Subclocks generated
PLL_OUT
PLL_OUT
Wander < 128 Hz Passed to Output
SDATA
SDATA
Wander and Jitter > 1 Hz Rejected
MCLK
LRCK
SCLK
MCLK
LRCK
SCLK
Jitter > 128 Hz Rejected
CS2300-OTP
D0
D0
DS844F1
D1
D1