CDK2000 Cirrus Logic, Inc., CDK2000 Datasheet - Page 8

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CDK2000

Manufacturer Part Number
CDK2000
Description
Fractional-n Clock Multiplier with Internal LCO
Manufacturer
Cirrus Logic, Inc.
Datasheet
8
PLL PERFORMANCE PLOTS
Test Conditions (unless otherwise specified): VD = 3.3 V; T
f
AuxOutSrc[1:0] = 11.
CLK_OUT
Samples size = 2.5M points; Base Band Jitter (10Hz to 40kHz).
10,000
1,000
100
0.1
10
1
1
Figure 2. CLK_IN Sinusoidal Jitter Tolerance
= 12.288 MHz; f
10
Input Jitter Frequency (Hz)
100
CLK_IN
1000
Figure 4. CLK_IN Random Jitter Rejection and Tolerance
0.01
100
0.1
10
1
0.01
= 12.288 MHz; Sample size = 10,000 points; Base Band Jitter (100 Hz to 40 kHz);
1,000
1 Hz Bandwidth
128 Hz Bandwidth
0.1
1 Hz Bandwidth
128 Hz Bandwidth
10,000
Input Jitter Level (nsec)
1
A
10
Samples size = 2.5M points; Base Band Jitter (10Hz to 40kHz).
= 25 °C (Commercial Grade); C
-10
-20
-30
-40
-50
-60
10
0
1
Figure 3. CLK_IN Sinusoidal Jitter Transfer
100
Unlock
Unlock
10
Input Jitter Frequency (Hz)
1000
100
L
1000
= 15 pF;
CS2300-OTP
1 Hz Bandwidth
128 Hz Bandwidth
10000
DS844F1

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