CDK2000 Cirrus Logic, Inc., CDK2000 Datasheet - Page 20

• Manufacturer Part Number: CDK2000
• Description: Fractional-n Clock Multiplier with Internal LCO
• Manufacturer: Cirrus Logic, Inc.

20
6.1.2
6.2
6.3
6.3.1
6.3.2
6.3.3
Ratio 0 - 3
The four 32-bit User Defined Ratios are stored in the CS2300’s one time programmable memory. See
put to Input Frequency Ratio Configuration” on page 13
page 22
Global Configuration Parameters
Auxiliary Output Source Selection (AuxOutSrc[1:0])
Selects the source of the AUX_OUT signal.
Note:
Lock Output Configuration (AuxLockCfg)” on page
AUX PLL Lock Output Configuration (AuxLockCfg)
When the AUX_OUT pin is configured as a lock indicator ( AuxOutSrc[1:0] modal parameter = ‘11’), this
global parameter configures the AUX_OUT driver to either push-pull or open drain. It also determines the
polarity of the lock signal. If AUX_OUT is configured as a clock output, the state of this parameter is dis-
regarded.
Note:
fore, the pin polarity is defined relative to the un lock condition.
Enable PLL Clock Output on Unlock (ClkOutUnl)
Defines the state of the PLL output during the PLL unlock condition.
Low-Frequency Ratio Configuration (LFRatioCfg)
Determines how to interpret the currently indexed 32-bit User Defined Ratio .
AuxOutSrc[1:0]
00
01
10
11
Application:
AuxLockCfg
0
1
Application:
ClkOutUnl
0
1
Application:
LFRatioCfg
0
1
Application:
for more details.
When set to 11, the AuxLockCfg global parameter sets the polarity and driver type
AUX_OUT is an un lock indicator, signalling an error condition when the PLL is unlocked. There-
Auxiliary Output Source
Reserved.
CLK_IN.
CLK_OUT.
PLL Lock Status Indicator.
“Auxiliary Output” on page 16
AUX_OUT Driver Configuration
Push-Pull, Active High (output ‘high’ for unlocked condition, ‘low’ for locked condition).
Open Drain, Active Low (output ‘low’ for unlocked condition, high-Z for locked condition).
“Auxiliary Output” on page 16
Clock Output Enable Status
Clock outputs are driven ‘low’ when PLL is unlocked.
Clock outputs are always enabled (results in unpredictable output when PLL is unlocked).
“PLL Clock Output” on page 15
Ratio Bit Encoding Interpretation
20.12 - High Multiplier.
12.20 - High Accuracy.
“User Defined Ratio (RUD)” on page 13
20).
and
“Calculating the User Defined Ratio” on
CS2300-OTP
(“AUX PLL
DS844F1
“Out-