CDK2000 Cirrus Logic, Inc., CDK2000 Datasheet - Page 21

• Manufacturer Part Number: CDK2000
• Description: Fractional-n Clock Multiplier with Internal LCO
• Manufacturer: Cirrus Logic, Inc.

DS844F1
6.3.4
6.3.5
M2 Pin Configuration (M2Config[2:0])
Controls which special function is mapped to the M2 pin
Clock Input Bandwidth (ClkIn_BW[2:0])
Sets the minimum loop bandwidth when locked to CLK_IN.
M2Config[2:0]
000
001
010
011
100
101
110
111
Application:
ClkIn_BW[2:0]
000
001
010
011
100
101
110
111
Application:
M2 pin function
Disable CLK_OUT pin.
Disable AUX_OUT pin.
Disable CLK_OUT and AUX_OUT.
RModSel[1:0] Modal Parameter Enable.
Reserved.
Reserved.
Reserved.
Force AuxOutSrc[1:0] = 10 (PLL Clock Out).
“M2 Mode Pin Functionality” on page 17
Minimum Loop Bandwidth
1 Hz
2 Hz
4 Hz
8 Hz
16 Hz
32 Hz
64 Hz
128 Hz
“Adjusting the Minimum Loop Bandwidth for CLK_IN” on page 11
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CS2300-OTP
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