XC9500XV Xilinx Corp., XC9500XV Datasheet - Page 12

• Manufacturer Part Number: XC9500XV
• Description: XC9500XV 2.5 V CPLD Family
• Manufacturer: Xilinx Corp.

XC9500XV Family High-Performance CPLD
12
PIN
0
V
CCIO
1.2V
Voltage
Output
Set to PIN
during valid user
operation
0
Figure 13: Bus-Hold Logic
Standard
Figure 12: Output Slew-Rate Control For (a) Rising and (b) Falling Outputs
T
SLEW
Drive to
V
CCIO
(a)
Level
Slew-Rate Limited
R
BH
DS049_13_041400
I/O
www.xilinx.com
1-800-255-7778
Time
Output Banking
XC95288XV and XC95144XV devices are designed with a
split-rail I/O structure. This permits the utilization of multiple
output drive levels for systems able to operate best in that
environment. The output partitioning is by function blocks
(FB). With this arrangement, designers can have some sets
of outputs driving to 2.5V and others set to 1.8V. Naturally, it
is possible to tie all rails to a single output voltage and get all
outputs driving to that level. Should designs be migrated
from one density to another in the same package, care
should be taken to remember the voltage assignments cho-
sen at the outset to assure consistency
Figure 14: Split Rail V
1.2V
Voltage
Output
V
CCIO1
0
XC95144XV and XC95288XV Devices
T
SLEW
Standard
Slew-Rate Limited
CC
V
GNDs
Output Power Connections in
CCINTs
Preliminary Product Specification
(b)
DS049 (v2.1) June 24, 2002
(Figure
DS049_14_011501
DS049_12_041400
V
14).
CCIO2
Time
R