XC9500XV Xilinx Corp., XC9500XV Datasheet - Page 5
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XC9500XV
Manufacturer Part Number
XC9500XV
Description
XC9500XV 2.5 V CPLD Family
Manufacturer
Xilinx Corp.
Datasheet
1.XC9500XV.pdf
(18 pages)
All global control signals are available to each individual
macrocell, including clock, set/reset, and output enable sig-
nals. As shown in
originates from either of three global clocks or a product
DS049 (v2.1) June 24, 2002
Preliminary Product Specification
I/O/GCK2
I/O/GCK3
I/O/GCK1
I/O/GSR
R
Figure
4, the macrocell register clock
Figure 4: Macrocell Clock and Set/Reset Capability
Product Term Set
Product Term Clock
Product Term Reset
Global Set/Reset
Global Clock 1
Global Clock 2
Global Clock 3
www.xilinx.com
1-800-255-7778
term clock. Both true and complement polarities of the
selected clock source can be used within each macrocell. A
GSR input is also provided to allow user registers to be set
to a user-defined state.
XC9500XV Family High-Performance CPLD
D/T
EC
S
R
Macrocell
DS049_04_041400
5