XC9500XV Xilinx Corp., XC9500XV Datasheet - Page 15

• Manufacturer Part Number: XC9500XV
• Description: XC9500XV 2.5 V CPLD Family
• Manufacturer: Xilinx Corp.

Table 4: Timing Model Parameters
DS049 (v2.1) June 24, 2002
Preliminary Product Specification
Notes:
1.
Propagation Delay
Global Clock Setup Time
Global Clock-to-output
Product Term Clock Setup
Time
Product Term
Clock-to-Output
Internal System Cycle
Period
S = the logic span of the function, as defined in the text.
Description
T
PSU
R
Setup Time = T
Propagation Delay = T
Combinatorial
P-Term Clock
Combinatorial
Logic
Logic
Path
(a)
PSU
(c)
Parameter
T
PD
Clock to Out Time = T
SYSTEM
T
T
T
T
T
PCO
PSU
CO
PD
SU
D/T Q
Figure 16: Basic Timing Model
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T
1-800-255-7778
PCO
Product Term
Allocator
PCO
+ T
+ T
+ T
+ T
PTA
PTA
PTA
PTA
-
-
*
*
*
*
S
S
S
S
(1)
Setup Time = T
Internal System Cycle Time = T
Combinatorial
Low-Power Setting
XC9500XV Family High-Performance CPLD
Combinatorial
Logic
Macrocell
Logic
+ T
+ T
+ T
+ T
-
-
SU
LP
LP
LP
LP
(b)
(d)
Clock to Out Time = T
D/T Q
D/T Q
Slew-Limited
SYSTEM
DS049_16_061200
+ T
+ T
+ T
Output
Setting
T
CO
SLEW
SLEW
SLEW
-
-
-
CO
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