ADAV803 Analog Devices, ADAV803 Datasheet - Page 18

• Manufacturer Part Number: ADAV803
• Description: Audio Codec
• Manufacturer: Analog Devices

ADAV803
DAC SECTION
The ADAV803 has two DAC channels arranged as a stereo
with single-ended analog outputs. Each channel has its own
independently programmable attenuator, adjustable in 1
of 0.375 dB per step. The DAC can receive data from the
playback or auxiliary input ports, the SRC, the ADC, or the DIR.
Each analog output pin sits at a dc level of VREF, and swings 1.0
V rms for a 0 dB digital input signal. A single op amp third-
order external low-pass filter is recommen
frequency noise present on the output pins. Note that the use of
op amps with low slew rate or low bandwidth can cause high
frequency noise and tones to fold down into the audio band.
Care should be taken in selecting these components.
The FILTD and FILTR pins should be bypassed by external
capacitors to AGND. The FILTD pin is used to reduce th
of the internal DAC bias circuitry, thereby reducing the DAC
output noise. The voltage at the VREF pin, FILTR, can be use
to bias external op amps used to filter the output signals. For
applications in which the FILTR is required to drive exter
op amps, which might draw mor than 50 µA or have dynamic
load changes, extra buffering should be used to preserve the
qua
The digital input data source for the DAC c
a number of available sources by programming the appropriate
bits in the datapath control register. Figure 27 shows how the
digital data source and the MCLK source for the DAC are
selected. Each DAC has an independent volume register giving
256 steps of control, with each step giving approximately 0
dB of attenuation. Note that the DACs are muted by def
prevent unwanted pops, clicks, and other noises from appearing
on the outputs while the ADAV803 is being configured. Each
DAC also has a peak-level register that records the peak value of
the digital audio data. Reading the register clears the peak.
lity of the ADAV803 reference.
ANALOG
OUTPUT
e
DAC
DAC
ded to remove high
an be selected from
MODULATOR
MULTI-BIT
Σ-∆
ault to
28 steps
e noise
Figure 28. DAC Block Diagram
nal
TO ZERO FLAG PINS
.375
pair
Rev. 0 | Page 18 of 56
d
INTERPOLATOR
TO CONTROL
REGISTERS
S
Correct operation of the DAC is dependent upon the data rate
provided to the DAC, the master clock applied to the DAC, and
the selected interpolation rate. By default, the DAC assumes that
the MCLK rate is 256 times the sample rate, which requires an
8-times oversampling rate. This combination is suitable for
sample rates of up to 48 kHz.
For a 96 kHz data rate that has a 24.576 MHz MCLK (256 × f
associated with it, the DAC MCLK divider should be set to
divide the MCLK by 2. This prevents the DAC engine from
running too fast. To compensate for the reduced MCLK rate, the
interpolator should be selected to operate in 4 × (DAC MCLK =
128 × f
sample rates.
electing a Sample Rate
VOLUME/MUTE
ZERO DETECT
S
DETECTOR
CONTROL
). Similar combinations can be selected for different
PEAK
Figure 27. Clock and Datapath Control on the DAC
DIVIDER
MCLK
MCLK
DAC
DAC
INPUT
DAC
FROM DAC
DATA PATH
MULTIPLEXER
REG 0x65
BITS 3–2
REG 0x76
BITS 7–5
REG 0x63
BITS 5–3
ADC
AUXILIARY IN
PLAYBACK
DIR
S
)