ADAV803 Analog Devices, ADAV803 Datasheet - Page 25

• Manufacturer Part Number: ADAV803
• Description: Audio Codec
• Manufacturer: Analog Devices

Ta
Address
N
N + 1
N + 2
N + 3
N + 4
N + 5
N + 6
N + 7
N + 8
N + 9
N + 10
N + 11
N + 12
N + 13
N + 14
N + 15
N + 16
N + 17
N + 18
N + 19
N + 20
N + 21
N + 22
N + 23
N = 0x20 for receiver channel status buffer.
N = 0x38 for transmitter channel status buffer.
The standards allow the channel status bits in each subframe to
be independent, but ordinarily the channel status bit in the two
subframes of each frame are the same. The channel status bits
are defined differently for the consumer audio standards and
the professional audio standards. The 192 channel status bits are
organized into 24 bytes and have the interpretations shown in
Table 9 and Table 10.
The SPDIF transmitter and receiver have a comprehensive
register set. The registers give the user full access to the
functions of the SPDIF block, such as detecting nonaudio and
validity bits, Q subcodes, preambles, and so on. The channel
status bits as defined by the IEC60958 and AES3 specifications
are stored in register buffers for ease of use. An autobuffering
function allows channel status bits and user bits read by the
receiver to be copied directly to the transmitter block, removing
the need for user intervention.
Receiver Section
The ADAV803 uses a double-buffering scheme to handle read-
ing channel status and user bit information. The channel status
bits are available as a memory buffer, taking up 24 consecutive
register locations. The user bits are read using an indirect
memory addressing scheme, where the receiver user- bit
indirect-address register is programmed with an offset to the
ble 10. Profess
7
Sc
in
Alignm
Frequency
f
S
al-
Samp
g
Le
User Bit Management
Alphanumeric Channel Destination Data—First Character
Alphanumeric Channel Destination Data—Last Character
vel
Reliability Flags
ent
le
Alphanumeric Channel Origin Data—First Character
Alphanumeric Channel Origin Data—Last Character
ional Audio Standard
6
Cyclic Redundancy Check Character (CRCC)
Sample Frequency (f
Alphanume
Alphanumeric Channel Destination Data
Alphanumeric Channel Origin Data
A
Local Sample Address Code—MSW
Lock
Local Sample Address Code—LSW
Source Word Length
lphanumeric Channel Origin Data
5
Local Sample Address Code
Local Sample Address Code
Time of Day Code—MSW
Time of Day Code—LSW
Chann
Time of Day Code
Time of Day Code
ric Channel Destination Data
4
Data Bits
el Identification
Reserved
Emphasis
S
)
3
Reserved
Channel Mode
Use of Auxilia
2
Reserved
Sample
Audio
Non-
Digital Audio
1
Reference
Bits
ry Mode
Signal
Rev. 0 | Page 25 of 56
Pro/
Con
= 1
0
user bit buffer, and the rece
to determine the user bits at that location. Reading the receiv
user bit data register automatically updates the indirect address
register to the next location in the buffer. Typically, the receiver
user bit indirect-address register is programmed to zero (the
start of the buffer), and the receiver user bit data register is
repeatedly until all the buffer’s data has been read. Figure 46 an
Figure 47 show how receiving the channel status bits and user
bits is implemented.
The SPDIF receive buffer is updated continuously by the
incoming SPDIF stream. Once all the channel status bits for th
block (192 for Channel A and 192 for Channel B) are received,
the bits are copied into the receiver channel status buffer. This
buffer stores all 384 bits of channel status information, and the
RxCSSWITCH bit in the channel status switch buffer register
determines whether the Channel A or the Channel B status bits
are required to be read. The receive channel status bit buffer is
24 bytes long and spans the address range from 0x20 to 0x
Because the channel status bits of an SPDIF stream rarely
change, a softw
notify
bit
inf
of th
re
The si
RxB
sh
ceiver b ffer co
own in Table 11.
s is av
ormat
CON
e RxCSBINT
ze o the user b
BUFFER
SPDIFIN
th
16.....23
8.....15
FIRST
0.....7
aila
e host
ion
FIRST BUFFER
u
F0
f
RECEIVE
BUFFER
ble or
have
DIRIN
bit in
SPDIF
are nterrupt/flag bit, RxCSBINT, is provided to
co
ntrol that either a new block of channel status
nfiguration register.
changed from a previous block. The function
Figure 47. Receiver User Bit Buffer
that the first five bytes of channel statu
is controlled by the RxBCONF3 bit in t
the receiver buffer configuration regis
Figure 46. Channel Status Buffer
i
USER-BIT
BUFFER
16.....23
it buffer can be set by programming
8.....15
0.....7
(24 × 8 BITS)
(24 × 8 BITS)
CHANNEL
STATUS A
CHANNEL
STATUS B
iver user bit data register can be read
ADDRESS = 0x50
ADDRESS = 0x51
RECEIVER USER BIT
RECEIVER USER BIT
INDIRECT ADDRESS
SECONDBUFFER
DATA REGISTER
CS BUFFER
RxCSSWITCH
(0x20–0x37)
REGISTER
RECEIVE
ADAV803
ter, as
s
he
the
37.
read
er
e
d