ADAV803 Analog Devices, ADAV803 Datasheet - Page 43

• Manufacturer Part Number: ADAV803
• Description: Audio Codec
• Manufacturer: Analog Devices

Table 47. Receiver Channel S
ADDRESS
RCSB7–0
Table 48. T
ADDRESS
TCSB7–0
Table 49. Receiver User Bit Buffer Indire
ADDRESS = 1010000 (0x50)
RxUBADDR07–00
Table 50. Receiver Us
ADDRESS = 1010001 (0x51)
RxUBDATA07–00
Table 51. Transmitte
ADDRESS = 1010010 (0x52)
TxUBADDR07–00
Table 52. Transmitter User Bit Buffer
ADDRESS = 1010011 (0x53)
TxUBDATA07–00
Table 53. Q Subcode CRCError Status Register (Read-Only)
ADDRESS = 1010100 (0x54)
QCRCERROR
QSUB
= 0100
= 0111000
ransmit
000 to 01
ter Ch
r User Bit Buffer
to 10
RxUBADDR07–RxUBADDR00
7, 6, 5, 4, 3, 2, 1, 0
Indirect address pointi
er Bit Buffer Data Register
RCS
7, 6, 5, 4, 3, 2, 1, 0
The 24-byte receiver channel status buffer. The PRO b
only if the channel status is not autob
TCS
7, 6, 5, 4, 3, 2, 1, 0
The 24-byte transmi
disa
RxUBDATA
7, 6, 5, 4, 3, 2, 1, 0
A read from this r
00. This buffer can be written to when autobuff
TxUBADDR07–TxU
7, 6, 5, 4, 3, 2, 1, 0
Indirect add
TxUBDATA
7, 6, 5, 4, 3, 2, 1, 0
A write to this register writes eight bits of user data to the transmit user bit buffer pointed to by TxUBADDR07–00.
When user bit autobuffering is enabled, this buffer is disabled.
RES
7
This bit is set, if the CRC check of the Q subcode fails. This bit remains high, but does not generate an interrupt. This
bit is cleared once the register is read.
This bit is set, if a Q subcode has been read into the Q subcode buffer (see Table 54).
annel Sta
B7–RC
B7–TCS
bled when
10111
01111 (0x
tatus Buffer
SB0
07–RxUBDATA00
07–TxUB
(0x20 to
B0
ress pointing to the address location in the transmitter user bit buffer.
tus Bu
RES
6
autob
38 to
egister reads eight bits of user data from the receiver user bit buffer pointed to by RxUBADDR07–
Indirect Address Register
Data Register
tter chann
ct Addr
BADDR00
ffer
0x37)
0x4F)
uffering b
DATA00
ng to th
ess Regi
RES
5
e addre
el stat
etwee
us buffer.
ster
n the rece
uffered
ss loca
Rev. 0 | Page 43 of 56
RES
4
tion in t
betwee
The PR
ering of the user bits is enabled; otherwise, it is a read-only buffer.
iver and transmitter is
he rece
n the re
O bit is s
it is store
RES
3
iver use
ceiver an
tored a
d at ad
r bit bu
t address
dress loca
d trans
enabled.
RES
2
ffer.
mitter.
location 0x38, Bit 0. This buffer is
tion 0
x20, Bit 0.
QCRCERROR
1
This bu
ffer is rea
ADAV803
QSUB
0
d