ADAV803 Analog Devices, ADAV803 Datasheet - Page 20

• Manufacturer Part Number: ADAV803
• Description: Audio Codec
• Manufacturer: Analog Devices

ADAV803
The worst-case images can be computed from the zero-order
hold frequency response:
where:
F is the frequency of the worst-case image that would be
2
f
The
192 kHz:
Hardware Model
The output rate of the low-pass filter in Figure 30 is the
interpolation rate:
Sampling at a rate of 201.3 GHz is clearly impractical, not to
mention the number of taps required to calculate each
interpolated sample. However, because interpolation by 2
involves zero-stuffing 2
most of the multiplies in the low-pass FIR filter are y ze
further reduction can be realize because only one interpolated
sample is ta
convolution needs to be performed per f
2
sufficient to suppress the images caused by the interpolation.
One difficulty with the above approach is that the correct
interpolated sample must be selected upon the arrival of f
Because there are 2
arrival of the f
1/201.3 GHz = 4.96 ps. Measuring the f
of 201.3 GHz frequency is clearly impossible; instead, several
coarse measurements of the f
averaged over time.
Another difficulty with the above approach is the number of
coefficients required. Because there are 2
tions with a 64-tap FIR filter, there must be 2
coefficients for each tap, which requires a total of 2
cients. To reduce the nu
stores a small subset of coefficients and performs a high order
interpolation between the stored coefficients.
The above approach works when f
the output sample rate, f
f
convolution must be scaled. As the input sample rate rises ove
the output sample rate, the antialiasing filter’s cutoff frequenc
S_INTERP
S_IN
20
20
× f
convolutions. A 64-tap FIR filter for each f
, the ROM starting address, input data, and length of the
following worst-case image
maximum image = sin (× F/f
Image at f
Image at f
2
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20
is f
× 192,000 kHz = 201.3 GHz
± f
S_IN
ken at the output at the f
S_IN
× 2
S_OUT
S_INTERP
S_INTERP
/2.
20
.
20
clock must be measured with an accuracy
possible convolutions per f
− 96 kH
+ 96 kHz = −125.1 dB
20
mber of coefficients in ROM, the SRC
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−1 samples between each f
, is less than the input sample rate,
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z = −125.1 dB
d,
s would appear for f
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clock period are made and
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S_OUT
S_OUT
> f
)/(× F/f
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20
rate, so only one
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possible convolu-
pe
20
. However, when
period instead of
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riod with a clock
polyphase
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sample is
26
S_IN
S_IN
b
coeffi
period,
)
sample,
equal to
ro.
20
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-
A
Rev. 0 | Page 20 of 56
the
y
of
r
.
must be lowered, because the Nyquist frequency of the ou
samples is less than the Nyquist frequency of the input samples.
To move the cutoff frequency of the antialiasing filter, the
coefficients are dynamically altered a
convolution is increased by a factor of (f
This technique is supported by the Fourier transform property
that, if f(t) is F(ω), then f(k × t) is F(ω/k). Thus, the range of
decimation is limited by the size of the RAM.
SRC Architecture
The architecture of the sample rate converter is shown in
Figure 32. The sample rate converter’s FIFO block adjusts the
left and right input samples and stores them for the FIR filter’s
convolution cycle. The f
to the FIFO block and the ramp input to the digital servo loop.
The ROM stores the coefficients for the FIR filter convolution
and performs a high order interpolation between the stored
coefficients. The sample rate ratio block measures the sample
rate for dynamically altering the ROM coefficients and scaling
o
servo loop auto ati
and provides the RAM and ROM start addresses for the s
the FIR filter convolution.
The FIFO receives the left and right input data and adjusts the
amplitude of the data for both the soft muting of the sample
rate converter and the scaling of the input data by the sample
rate ratio before storing the samples in the RAM. The input data
is scaled by the sample rate ratio, because, as the FIR filter
length of the convolution increases, so does the amplitude of the
convolution output. To keep the output of the FIR filter from
saturating, the input data is scaled down by multiplying it by
(f
data for muting and unmuting of the SRC.
The RAM in the FIFO is 512 words deep for both left and right
channels. An offset to the write address provided by the f
counter is added to prevent the RAM read pointer from
overlapping the write address. The minimum offset on the SRC
is 16 samples. However, the group delay and mute-in register
can be used to increase this offset.
f the FIR filter length as well as the input data. The digital
S_OUT
RIGHT DATA IN
LEFT DATA IN
COUNTER
/f
f
S_IN
S_IN
Figure 32. Architecture of the Sample Rate Converter
) when f
f
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f
S_IN
m cally tracks the f
SAMPLE RATE RATIO
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SERVO LOOP
RATE RATIO
SAMPLE
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DIGITAL
< f
FIFO
S_IN
counter provides the write address
. The FIFO also scales the input
EXTERNAL
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RATIO
nd the length of the
FIR FILTER
and f
ROM A
ROM B
ROM C
ROM D
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/f
S_OUT
S_OUT
L/R DATA OUT
).
INTERP
sample rates
ORDER
HIGH
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tart of
tput