MT55L1MY18P Micron Semiconductor Products, Inc., MT55L1MY18P Datasheet - Page 5

• Manufacturer Part Number: MT55L1MY18P
• Description: 18Mb ZBT SRAM, 3.3V Vdd, 2.5V or 3.3V I/O; 2.5V Vdd, 2.5V I/O, Pipelined,
• Manufacturer: Micron Semiconductor Products, Inc.

Table 1:
18Mb: 1 Meg x 18, 512K x 32/36 Pipelined ZBT SRAM
MT55L1MY18P_16_D.fm – Rev. D, Pub. 2/03
MODE (LBO#)
SYMBOL
ADV/LD#
OE# (G#)
NF/DQPa
NF/DQPb
NF/DQPd
NF/DQPc
BWa#
BWb#
BWd#
BWc#
V
R/W#
CE2#
CKE#
DQa
DQb
DQd
DQc
CLK
SA0
SA1
V
CE#
CE2
V
SA
DD
ZZ
DD
SS
Q
TQFP Pin Descriptions
Output
Supply
Supply
Supply
Input/
TYPE
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
I/O
NF
Synchronous Address Advance/Load: When HIGH, this input is used to advance the internal
burst counter, controlling burst access after the external address is loaded. When ADV/LD# is
HIGH, R/W# is ignored. A LOW on ADV/LD# clocks a new address at the CLK rising edge.
Synchronous Byte Write Enables: These active LOW inputs allow individual bytes to be
written when a WRITE cycle is active and must meet the setup and hold times around the
rising edge of CLK. BWs need to be asserted on the same cycle as the address. BWs are
associated with addresses and apply to subsequent data. BWa# controls DQa pins; BWb#
controls DQb pins; BWc# controls DQc pins; BWd# controls DQd pins.
Synchronous Chip Enable: This active LOW input is used to enable the device and is sampled
only when a new external address is loaded (ADV/LD# LOW).
Synchronous Chip Enable: This active LOW input is used to enable the device and is sampled
only when a new external address is loaded (ADV/LD# LOW). This input can be used for
memory depth expansion.
Synchronous Chip Enable: This active HIGH input is used to enable the device and is sampled
only when a new external address is loaded (ADV/LD# LOW). This input can be used for
memory depth expansion.
Synchronous Clock Enable: This active LOW input permits CLK to propagate throughout the
device. When CKE# is HIGH, the device ignores the CLK input and effectively internally
extends the previous CLK cycle. This input must meet setup and hold times around the rising
edge of CLK.
Clock: This signal registers the address, data, chip enables, byte write enables, and burst
control inputs on its rising edge. All synchronous inputs must meet setup and hold times
around the clock’s rising edge.
Mode: This input selects the burst sequence. A LOW on this pin selects linear burst. NC or
HIGH on this pin selects interleaved burst. Do not alter input state while device is operating.
LBO# is the JEDEC-standard term for MODE.
Output Enable: This active LOW, asynchronous input enables the data I/O output drivers. G#
is the JEDEC-standard term for OE#.
Read/Write: This input determines the cycle type when ADV/LD# is LOW and is the only
means for determining READs and WRITEs. READ cycles may not be converted into WRITEs
(and vice versa) other than by loading a new address. A LOW on this pin permits BYTE WRITE
operations and must meet the setup and hold times around the rising edge of CLK. Full bus-
width WRITEs occur if all byte write enables are LOW.
Synchronous Address Inputs: These inputs are registered and must meet the setup and hold
times around the rising edge of CLK. SA0 and SA1 are the two least significant bits (LSB) of
the address field and set the internal burst counter if burst is desired.
Snooze Enable: This active HIGH, asynchronous input causes the device to enter a low-power
standby mode in which all data in the memory array is retained. When ZZ is active, all other
inputs are ignored. This pin has an internal pull-down and can be left unconnected.
SRAM Data I/Os: Byte “a” associated with is DQa pins; byte “b” is associated with DQb pins;
byte “c” is associated with DQc pins; byte “d” is associated withDQd pins. Input data must
meet setup and hold times around the rising edge of CLK.
No Function/Parity Data I/Os: On the x32 version, these are No Function (NF). On the x18
version, byte “a” parity is DQPa; byte “b” parity is DQPb. On the x36 version, byte “a” parity
is DQPa; byte “b” parity is DQPb; byte “c” parity is DQPc; byte “d” parity is DQPd.
Power Supply: See DC Electrical Characteristics and Operating Conditions for range.
Isolated Output Buffer Supply: See DC Electrical Characteristics and Operating Conditions for
range.
Ground: GND.
5
18Mb: 1 MEG x 18, 512K x 32/36
DESCRIPTION
Micron Technology, Inc., reserves the right to change products or specifications without notice.
PIPELINED ZBT SRAM
©2003 Micron Technology, Inc.