MT58L128L18P Micron Semiconductor Products, Inc., MT58L128L18P Datasheet

MT58L128L18P

Manufacturer Part Number

MT58L128L18P

Description

2Mb Syncburst SRAM, 3.3V Vdd, 3.3V or 2.5V I/O, Pipelined, Scd,

Manufacturer

Micron Semiconductor Products, Inc.

Datasheet

1.MT58L128L18P.pdf (20 pages)

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NOT RECOMENDED FOR NEW DESIGNS

2Mb SYNCBURST

SRAM

FEATURES

• Fast clock and OE# access times

• Single +3.3V +0.3V/-0.165V power supply (V

• Separate +3.3V or +2.5V isolated output buffer

• SNOOZE MODE for reduced-power standby

• Single-cycle deselect (Pentium

• Common data inputs and data outputs

• Individual BYTE WRITE control and GLOBAL

• Three chip enables for simple depth expansion

• Clock-controlled and registered addresses, data

• Internally self-timed WRITE cycle

• Burst control pin (interleaved or linear burst)

• Automatic power-down for portable applications

• 100-pin TQFP package

• Low capacitive bus loading

• x18, x32, and x36 options available

OPTIONS

• Timing (Access/Cycle/MHz)

• Configurations

• Package

• Operating Temperature Range

2Mb: 128K x 18, 64K x 32/36 Pipelined, SCD SyncBurst SRAM

MT58L128L18P_C.p65 – Rev. C, Pub. 11/02

supply (V

WRITE

and address pipelining

I/Os and control signals

3.5ns/5ns/200 MHz

3.5ns/6ns/166 MHz

4.0ns/7.5ns/133 MHz

5ns/10ns/100 MHz

3.3V I/O

2.5V I/O

100-pin TQFP

Commercial (0°C to +70°C)

128K x 18

64K x 32

64K x 36

64K x 32

64K x 36

PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.

MT58L128L18PT-10

Part Number Example:

BSRAM-compatible)

MT58L128V18P

MT58L128L18P

MT58L64V32P

MT58L64V36P

MT58L64L32P

MT58L64L36P

MARKING

None

-7.5

-10

™

-5

-6

)

PIPELINED, SCD SYNCBURST SRAM

MT58L128L18P, MT58L64L32P, MT58L64L36P;

MT58L128V18P, MT58L64V32P, MT58L64V36P

3.3V V

Cycle Deselect

GENERAL DESCRIPTION

high-speed, low-power CMOS designs that are fabri-

cated using an advanced CMOS process.

18, 64K x 32, or 64K x 36 SRAM core with advanced

synchronous peripheral circuitry and a 2-bit burst

counter. All synchronous inputs pass through registers

controlled by a positive-edge-triggered single clock

input (CLK). The synchronous inputs include all

addresses, all data inputs, active LOW chip enable (CE#),

two additional chip enables for easy depth expansion

(CE2, CE2#), burst control inputs (ADSC#, ADSP#,

ADV#), byte write enables (BWx#), and global write

(GW#).

(OE#), clock (CLK), and snooze enable (ZZ). There is

also a burst mode pin (MODE) that selects between

interleaved and linear burst modes. The data-out (Q),

enabled by OE#, is also asynchronous. WRITE cycles

can be from one to two bytes wide (x18) or from one

to four bytes wide (x32/x36), as controlled by the write

control inputs.

status processor (ADSP#) or address status controller

(ADSC#) input pins. Subsequent burst addresses can be

internally generated as controlled by the burst advance

pin (ADV#).

*JEDEC-standard MS-026 BHA (LQFP).

The Micron

Micron’s 2Mb SyncBurst SRAMs integrate a 128K x

Asynchronous inputs include the output enable

Burst operation can be initiated with either address

2Mb: 128K x 18, 64K x 32/36

, 3.3V or 2.5V I/O, Pipelined, Single-

100-Pin TQFP*

SyncBurst

™

SRAM family employs

Related parts for MT58L128L18P

MT58L128L18P Summary of contents

Page 1

... Operating Temperature Range Commercial (0°C to +70°C) Part Number Example: MT58L128L18PT-10 2Mb: 128K x 18, 64K x 32/36 Pipelined, SCD SyncBurst SRAM MT58L128L18P_C.p65 – Rev. C, Pub. 11/02 PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. 2Mb: 128K x 18, 64K x 32/36 PIPELINED, SCD SYNCBURST SRAM ™ ...

Page 2

... CE2# OE# NOTE: Functional block diagrams illustrate simplified device operation. See truth table, pin descriptions, and timing diagrams for detailed information. 2Mb: 128K x 18, 64K x 32/36 Pipelined, SCD SyncBurst SRAM MT58L128L18P_C.p65 – Rev. C, Pub. 11/02 PIPELINED, SCD SYNCBURST SRAM FUNCTIONAL BLOCK DIAGRAM 128K ...

Page 3

... Connect (NC) is used on the x32 version. Parity (DQPx) is used on the x36 version. 2Mb: 128K x 18, 64K x 32/36 Pipelined, SCD SyncBurst SRAM MT58L128L18P_C.p65 – Rev. C, Pub. 11/02 2Mb: 128K x 18, 64K x 32/36 PIPELINED, SCD SYNCBURST SRAM deselected after a READ cycle, the output bus goes to a High-Z state of clock ...

Page 4

... Connect (NC) is used on the x32 version. Parity (DQPx) is used on the x36 version. 2Mb: 128K x 18, 64K x 32/36 Pipelined, SCD SyncBurst SRAM MT58L128L18P_C.p65 – Rev. C, Pub. 11/02 PIPELINED, SCD SYNCBURST SRAM PIN ASSIGNMENT (Top View) 100-Pin TQFP ...

Page 5

... ADV ADSP# 2Mb: 128K x 18, 64K x 32/36 Pipelined, SCD SyncBurst SRAM MT58L128L18P_C.p65 – Rev. C, Pub. 11/02 PIPELINED, SCD SYNCBURST SRAM TYPE SA0 Input Synchronous Address Inputs: These inputs are registered and must SA1 meet the setup and hold times around the rising edge of CLK. ...

Page 6

... NC/SA 2Mb: 128K x 18, 64K x 32/36 Pipelined, SCD SyncBurst SRAM MT58L128L18P_C.p65 – Rev. C, Pub. 11/02 PIPELINED, SCD SYNCBURST SRAM TYPE Input Synchronous Address Status Controller: This active LOW input interrupts any ongoing burst, causing a new external address to be registered. A READ or WRITE is performed using the new address if CE# is LOW ...

Page 7

... WRITE All Bytes WRITE All Bytes NOTE: Using BWE# and BWa# through BWd#, any one or more bytes may be written. 2Mb: 128K x 18, 64K x 32/36 Pipelined, SCD SyncBurst SRAM MT58L128L18P_C.p65 – Rev. C, Pub. 11/02 2Mb: 128K x 18, 64K x 32/36 PIPELINED, SCD SYNCBURST SRAM X...X01 X...X10 X ...

Page 8

... ADSP# LOW always initiates an internal READ at the L-H edge of CLK. A WRITE is performed by setting one or more byte write enable signals and BWE# LOW or GW# LOW for the subsequent L-H edge of CLK. Refer to WRITE timing diagram for clarification. 2Mb: 128K x 18, 64K x 32/36 Pipelined, SCD SyncBurst SRAM MT58L128L18P_C.p65 – Rev. C, Pub. 11/02 PIPELINED, SCD SYNCBURST SRAM ZZ USED ...

Page 9

... V Q should never exceed V DD 2Mb: 128K x 18, 64K x 32/36 Pipelined, SCD SyncBurst SRAM MT58L128L18P_C.p65 – Rev. C, Pub. 11/02 PIPELINED, SCD SYNCBURST SRAM *Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional ...

Page 10

... than the shown DC values. AC I/O curves are available upon request should never exceed V DD 2Mb: 128K x 18, 64K x 32/36 Pipelined, SCD SyncBurst SRAM MT58L128L18P_C.p65 – Rev. C, Pub. 11/02 PIPELINED, SCD SYNCBURST SRAM Q = +2.5V +0.4V/-0.125V unless otherwise noted) DD CONDITIONS SYMBOL Data bus (DQx) V Inputs 0V ≤ ...

Page 11

... Typical values are measured at 3.3V, 25°C and 10ns cycle time. 5. This parameter is sampled. 2Mb: 128K x 18, 64K x 32/36 Pipelined, SCD SyncBurst SRAM MT58L128L18P_C.p65 – Rev. C, Pub. 11/02 PIPELINED, SCD SYNCBURST SRAM = +3.3V +0.3V/-0.165V unless otherwise noted) CONDITIONS SYM ...

Page 12

... Thermal Resistance (Junction to Top of Case) NOTE: 1. Typical values are measured at 3.3V, 25°C and 10ns cycle time. 2Mb: 128K x 18, 64K x 32/36 Pipelined, SCD SyncBurst SRAM MT58L128L18P_C.p65 – Rev. C, Pub. 11/02 PIPELINED, SCD SYNCBURST SRAM CONDITIONS and procedures for measuring thermal impedance, per EIA/JESD51. ...

Page 13

... Chip enable must be valid at each rising edge of CLK when either ADSP# or ADSC# is LOW to remain enabled. 2Mb: 128K x 18, 64K x 32/36 Pipelined, SCD SyncBurst SRAM MT58L128L18P_C.p65 – Rev. C, Pub. 11/02 PIPELINED, SCD SYNCBURST SRAM = +3.3V +0.3V/-0.165V) ...

Page 14

... SyncBurst SRAM timing is dependent upon the capaci- tive loading on the outputs. Consult the factory for copies of I/O current versus voltage curves. 2Mb: 128K x 18, 64K x 32/36 Pipelined, SCD SyncBurst SRAM MT58L128L18P_C.p65 – Rev. C, Pub. 11/02 PIPELINED, SCD SYNCBURST SRAM 2.5V I/O AC TEST CONDITIONS = (V /2.2) + 1.5V Input pulse levels ............. V ...

Page 15

... ISB2Z ALL INPUTS (except ZZ) Outputs (Q) 2Mb: 128K x 18, 64K x 32/36 Pipelined, SCD SyncBurst SRAM MT58L128L18P_C.p65 – Rev. C, Pub. 11/02 2Mb: 128K x 18, 64K x 32/36 PIPELINED, SCD SYNCBURST SRAM The ZZ pin is an asynchronous, active HIGH input that causes the device to enter SNOOZE MODE. When the ZZ pin becomes a logic HIGH, I ...

Page 16

... Timing is shown assuming that the device was not enabled before entering into this sequence. OE# does not cause driven until after the following clock rising edge. 4. Outputs are disabled within one clock cycle after deselect. 2Mb: 128K x 18, 64K x 32/36 Pipelined, SCD SyncBurst SRAM MT58L128L18P_C.p65 – Rev. C, Pub. 11/02 PIPELINED, SCD SYNCBURST SRAM READ TIMING t ADSS ...

Page 17

... Full-width WRITE can be initiated by GW# LOW; or GW# HIGH and BWE#, BWa# and BWb# LOW for x18 device; or GW# HIGH and BWE#, BWa#-BWd# LOW for x32 and x36 devices. 2Mb: 128K x 18, 64K x 32/36 Pipelined, SCD SyncBurst SRAM MT58L128L18P_C.p65 – Rev. C, Pub. 11/02 PIPELINED, SCD SYNCBURST SRAM WRITE TIMING ...

Page 18

... The data bus (Q) remains in High-Z following a WRITE cycle unless an ADSP#, ADSC# or ADV# cycle is performed. 4. GW# is HIGH. 5. Back-to-back READs may be controlled by either ADSP# or ADSC#. 2Mb: 128K x 18, 64K x 32/36 Pipelined, SCD SyncBurst SRAM MT58L128L18P_C.p65 – Rev. C, Pub. 11/02 PIPELINED, SCD SYNCBURST SRAM READ/WRITE TIMING A3 ...

Page 19

... E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992 Micron, SyncBurst, the M logo, and the Micron logo are trademarks and/or service marks of Micron Technology, Inc. 2Mb: 128K x 18, 64K x 32/36 Pipelined, SCD SyncBurst SRAM MT58L128L18P_C.p65 – Rev. C, Pub. 11/02 PIPELINED, SCD SYNCBURST SRAM 100-PIN PLASTIC TQFP (JEDEC LQFP) 0.625 14.00 ± ...

Page 20

... Changed heading on Mechanical Drawing from BGA to FBGA Added 165-Pin FBGA package, REV 3/00, FINAL ..................................................................................... March/3/00 Added PRELIMINARY PACKAGE DATA to diagram 2Mb: 128K x 18, 64K x 32/36 Pipelined, SCD SyncBurst SRAM MT58L128L18P_C.p65 – Rev. C, Pub. 11/02 2Mb: 128K x 18, 64K x 32/36 PIPELINED, SCD SYNCBURST SRAM 20 Micron Technology, Inc., reserves the right to change products or specifications without notice. ...

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