MT58L1MY18F Micron Semiconductor Products, Inc., MT58L1MY18F Datasheet - Page 18

• Manufacturer Part Number: MT58L1MY18F
• Description: 18Mb Syncburst SRAM, 3.3V Vdd, 2.5V or 3.3V I/O; 2.5V Vdd, 2.5V I/O, Flow-Through,
• Manufacturer: Micron Semiconductor Products, Inc.

NOTE:
18Mb: 1 Meg x 18, 512K x 32/36, Flow-Through SyncBurst SRAM
MT58L1MY18F_16_D.fm – Rev. D, Pub. 2/03
BWE#, GW#,
BWa#-BWd#
1. Q(A2) refers to output from address A2. Q(A2 + 1) refers to output from the next internal burst address following
2. CE2# and CE2 have timing identical to CE#. On this diagram, when CE# is LOW, CE2# is LOW and CE2 is HIGH. When
3. Timing is shown assuming that the device was not enabled before entering into this sequence. (This note applies to
4. Outputs are disabled
ADDRESS
(NOTE 2)
A2.
CE# is HIGH, CE2# is HIGH and CE2 is LOW.
whole diagram.)
ADSP#
ADSC#
ADV#
OE#
CLK
CE#
Q
High-Z
t ADSS
t AS
t CES
A1
t ADSH
t KQLZ
t AH
t CEH
t KH
t
t OEQ
t KQ
KQHZ after deselect.
t KC
Single READ
t WS
t KL
Q(A1)
t WH
t OEHZ
t ADSS
A2
t ADSH
t OELZ
t AAS
(NOTE 1)
Q(A2)
t KQX
t AAH
READ Timing
t KQ
Figure 7:
Q(A2 + 1)
18
FLOW-THROUGH SYNCBURST SRAM
18Mb: 1 MEG x 18, 512K x 32/36
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Q(A2 + 2)
ADV# suspends burst.
BURST
READ
Q(A2 + 3)
Q(A2)
Burst wraps around
to its initial state
DON’T CARE
Q(A2 + 1)
©2003 Micron Technology, Inc.
Deselect Cycle
(Note 4)
UNDEFINED
Q(A2 + 2)
t KQHZ