MPC8260A Motorola, MPC8260A Datasheet - Page 22

• Manufacturer Part Number: MPC8260A
• Description: Micro Processor
• Manufacturer: Motorola

Clock Configuration Modes
1.3.2
This section pertains to the MPC8265A and the MPC8266A only.
In PCI mode only, MODCK_HI[0:3] and PCI_MODCK come from the following external pins:
1
2
3
4
22
MODCK_H–MODCK[1–3]
Because of speed dependencies, not all of the possible configurations in Table 15 are applicable.
The user should choose the input clock frequency and the multiplication factors such that the frequency of the
Input clock frequency is given only for the purpose of reference. User should set MODCK_H–MODCK_L so that
At this mode the CPU PLL is bypassed (the CPU frequency equals the bus frequency).
CPU is equal to or greater than150 MHz and the CPM ranges between 66–233 MHz.
the resulting configuration does not exceed the frequency rating of the user’s part.
Example. If a part is rated at 266 MHz CPU, 200 MHz CPM, and 66 MHz bus, any of the following are possible
(note that the three input clock frequencies are only three of many possible input clock frequencies):
1. 66 MHz input clock and MODCK_H–MODCK_L[0111–101] (with a core multiplication factor of 4 and a CPM
2. 50 MHz input clock and MODCK_H–MODCK_L[0111–101] to achieve a configuration of 200 MHz CPU,
3. 40 MHz input clock and MODCK_H–MODCK_L[0010–011] to achieve a configuration of 200 MHz CPU,
Note that with each example, any one of several values for MODCK_H–MODCK_L could possibly be used as
long as the resulting configuration does not exceed the part’s rating.
•
•
multiplication factor of 3). The resulting configuration equals the part’s maximum possible frequencies of
266 MHz CPU, 200 MHz CPM, and 66 MHz bus.
150 MHz CPM, and 50 MHz bus.
160 MHz CPM, and 40 MHz bus.
1100_000
1100_001
1100_010
PCI_MODCK = LGPL5
MODCK_HI[0:3] = {LGPL0,LGPL1,LGPL2,LGPL3}
0111_111
1000_000
1000_001
1000_010
1000_011
1000_100
PCI Mode
The minimum Tval = 2 when PCI_MODCK = 1 and minimum Tval = 1
when PCI_MODCK = 0; therefore, board designers should use clock
configurations that fit this condition to achieve PCI-compliant AC timing.
4
4
4
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Table 15. Clock Configuration Modes
Frequency
MPC826xA (HiP4) Family Hardware Specifications
Input Clock
66 MHz
66 MHz
66 MHz
66 MHz
66 MHz
66 MHz
66 MHz
66 MHz
66 MHz
2,3
CPM Multiplication
Factor
3.5
3.5
3.5
3.5
3.5
3.5
2.5
2
3
NOTE
2
Frequency
233 MHz
233 MHz
233 MHz
233 MHz
233 MHz
233 MHz
133 MHz
166 MHz
200 MHz
CPM
1
(Continued)
2
Core Multiplication
Factor
Bypass
Bypass
Bypass
2.5
3.5
4.5
2
3
4
2
MOTOROLA
Frequency
133 MHz
166 MHz
200 MHz
233 MHz
266 MHz
300 MHz
66 MHz
66 MHz
66 MHz
Core
2