MPC8260A Motorola, MPC8260A Datasheet - Page 6

• Manufacturer Part Number: MPC8260A
• Description: Micro Processor
• Manufacturer: Motorola

Features
Additional features of the MPC826xA family are as follows:
6
•
•
•
— Eight independent baud rate generators and 20 input clock pins for supplying clocks to FCCs,
— Four independent 16-bit timers that can be interconnected as two 32-bit timers
CPM
— 32-Kbyte dual-port RAM
— Additional MCC host commands
— Eight transfer transmission convergence (TC) layers between the TDMs and FCC2 to support
CPM multiplexing
— FCC2 can also be connected to the TC layer.
TC layer (MPC8264A and MPC8266A only)
— Each of the 8 TDM channels is routed in hardware to a TC layer block
— Operates with FCC2 (UTOPIA 8)
— Provides serial loop back mode
— Cell echo mode is provided
— Supports both FCC transmit modes
– Supports T1, CEPT, T1/E1, T3/E3, pulse code modulation highway, ISDN basic rate, ISDN
SCCs, SMCs, and serial channels
inverse multiplexing for ATM capabilities (IMA) (MPC8264A and MPC8266A only)
– Protocol-specific overhead bits may be discarded or routed to other controllers by the SI
– Performing ATM TC layer functions (according to ITU-T I.432)
– Transmit (Tx) updates
– Receive (Rx) updates
– External rate mode—Idle cells are generated by the FCC (microcode) to control data rate.
– Internal rate mode (sub-rate)—FCC transfers only the data cells using the required data rate.
primary rate, Motorola interchip digital link (IDL), general circuit interface (GCI), and
user-defined TDM serial interfaces
– Cell HEC generation
– Payload scrambling using self synchronizing scrambler (programmable by the user)
– Coset generation (programmable by the user)
– Cell rate by inserting idle/unassigned cells
– Cell delineation using bit by bit HEC checking and programmable ALPHA and DELTA
– Payload descrambling using self synchronizing scrambler (programmable by the user)
– Coset removing (programmable by the user)
– Filtering idle/unassigned cells (programmable by the user)
– Performing HEC error detection and single bit error correction (programmable by user)
– Generating loss of cell delineation status/interrupt (LOC/LCD)
The TC layer generates idle/unassigned cells to maintain the line bit rate.
parameters for the delineation state machine
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
MPC826xA (HiP4) Family Hardware Specifications
MOTOROLA